參數(shù)資料
型號: Q67120-C1056SAB-C501G-1EP
英文描述: IC-8-BIT CPU
中文描述: 集成電路8位CPU
文件頁數(shù): 107/121頁
文件大?。?/td> 1000K
代理商: Q67120-C1056SAB-C501G-1EP
Device Specifications
C501
Semiconductor Group
10-10
AC Characteristics for C501-L40 / C501-1R40
(cont’d)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
40 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 40 MHz
min.
6
t
CLCL
– 30
6
t
CLCL
– 30
t
CLCL
– 15
min.
max.
max.
RD pulse width
t
RLRH
t
WLWH
t
LLAX2
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
WHLH
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
120
ns
WR pulse width
120
ns
Address hold after ALE
10
5
t
CLCL
– 50
2
t
CLCL
– 12
8
t
CLCL
– 50
9
t
CLCL
– 75
3
t
CLCL
+ 15
t
CLCL
+ 15
ns
RD to valid data in
75
ns
Data hold after RD
0
0
ns
Data float after RD
38
ns
ALE to valid data in
150
ns
Address to valid data in
150
3
t
CLCL
– 15
4
t
CLCL
– 30
t
CLCL
– 15
t
CLCL
– 20
7
t
CLCL
– 50
t
CLCL
– 20
ns
ALE to WR or RD
60
90
ns
Address valid to WR or RD
70
ns
WR or RD high to ALE high
10
40
ns
Data valid to WR transition
5
ns
Data setup before WR
125
ns
Data hold after WR
5
ns
Address float after RD
0
0
ns
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 40 MHz
min.
max.
Oscillator period
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
25
285.7
t
CLCL
t
CLCX
t
CLCL
t
CHCX
10
ns
High time
10
ns
Low time
10
ns
Rise time
ns
Fall time
10
ns
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