參數(shù)資料
型號: Q67120-C1056SAB-C501G-1EP
英文描述: IC-8-BIT CPU
中文描述: 集成電路8位CPU
文件頁數(shù): 84/121頁
文件大?。?/td> 1000K
代理商: Q67120-C1056SAB-C501G-1EP
Semiconductor Group
7-6
Interrupt System
C501
7.1.3 Interrupt Priority Register
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in the SFR IP (Interrupt Priority, 0: low priority, 1: high priority).
Special Function Register IP (Address B8H)
Reset Value : XX000000B
The shaded bits are not used for interrupt control.
Bit
Function
Not implemented. Reserved for future use.
PT2
Timer 2 Interrupt Priority Level.
If PT2 = 0, the Timer 2 interrupt has a low priority.
PS
Serial Channel Interrupt Priority Level.
If PS = 0, the Serial Channel interrupt has a low priority.
PT1
Timer 1 Overflow Interrupt Priority Level.
If PT1 = 0, the Timer 1 interrupt has a low priority.
PX1
External Interrupt 1 Priority Level.
If PX1 = 0, the external interrupt 1 has a low priority.
PT0
Timer 0 Overflow Interrupt Priority Level.
If PT0 = 0, the Timer 0 interrupt has a low priority.
PX0
External Interrupt 0 Priority Level.
If PX0 = 0, the external interrupt 0 has a low priority.
MSB
7
LSB
0
PT2
PS
B8H
IP
PT1
PX1
PT0
PX0
Bit No.
6
5
4
3
2
1
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