參數(shù)資料
型號: Q67120-C1056SAB-C501G-1EP
英文描述: IC-8-BIT CPU
中文描述: 集成電路8位CPU
文件頁數(shù): 105/121頁
文件大小: 1000K
代理商: Q67120-C1056SAB-C501G-1EP
Device Specifications
C501
Semiconductor Group
10-8
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24
(cont’d)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter
Symbol
Limit Values
Unit
24 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 24 MHz
min.
6
t
CLCL
– 70
6
t
CLCL
– 70
t
CLCL
– 27
min.
max.
max.
RD pulse width
t
RLRH
t
WLWH
t
LLAX2
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
WHLH
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
180
ns
WR pulse width
180
ns
Address hold after ALE
15
5
t
CLCL
– 90
2
t
CLCL
– 20
8
t
CLCL
– 133
9
t
CLCL
– 155
3
t
CLCL
+ 50
t
CLCL
+ 25
ns
RD to valid data in
118
ns
Data hold after RD
0
0
ns
Data float after RD
63
ns
ALE to valid data in
200
ns
Address to valid data in
220
3
t
CLCL
– 50
4
t
CLCL
– 97
t
CLCL
– 25
t
CLCL
– 37
7
t
CLCL
– 122
t
CLCL
– 27
ns
ALE to WR or RD
75
175
ns
Address valid to WR or RD
67
ns
WR or RD high to ALE high
17
67
ns
Data valid to WR transition
5
ns
Data setup before WR
170
ns
Data hold after WR
15
ns
Address float after RD
0
0
ns
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min.
max.
Oscillator period
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
41.7
285.7
t
CLCL
t
CLCX
t
CLCL
t
CHCX
12
ns
High time
12
ns
Low time
12
ns
Rise time
ns
Fall time
12
ns
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