參數(shù)資料
型號(hào)： QR0001
文件頁(yè)數(shù)： 17/40頁(yè)
文件大小： 440K
代理商： QR0001
3.0 Client Interface
(Continued)
TABLE 3.12. Receive Symbol Register (Read Only)
31:0
The most recent 32 Bits of the RxS received.
Table 3.13 gives the decode for reading the various register
bits.
TABLE 3.13. Register Access Decode
RxSEL
[
3:0
]
RxNBL
[
3:0
]
RxS
[
3:0
]
RxS
[
7:4
]
RxS
[
11:8
]
RxS
[
15:12
]
RxS
[
19:16
]
RxS
[
23:20
]
RxS
[
27:24
]
RxS
[
31:28
]
Diagnostics
[
3:0
]
Diagnostics
[
7:4
]
Diagnostics
[
11:8
]
Diagnostics
[
15:12
]
Diagnostics
[
19:16
]
Diagnostics
[
23:20
]
Diagnostics
[
27:24
]
Diagnostics
[
31:28
]
Description
0
1
2
3
4
5
6
7
8
Node ID
9
No. of Nodes
10
Error Status
11
Syndrome Word
Syndrome Word
*
12
13
Reserved
14
Reserved
15
Reserved
*
Note:
Bit 19 is reserved.
3.15 Error Detection (see also Section 3.16)
The error detection code (EDC) field, CB
[
6:0
]
provides re-
dundant parity checking to verify symbol integrity. The
QR0001 implements a modified Hamming code algorithm
that provides Double Error Detection (DED).
To reduce latency effects, this version of the QR0001 pro-
vides the syndrome word that can be read from the Diag-
nostics register to show bit(s) detected in error.
The syndrome word, S
[
6:0
]
, consists of the Ex-OR of
the Incoming check bits that were sent within the pack-
et, CB
[
6:0
]
, and new generated check bits for the pack-
et (new generated, NGCB
[
6:0
]
).
A correct EDC field is transmitted with each symbol emitted
from the downstream port. Every symbol that is received at
the upstream port is passed through an EDC checking cir-
cuit. Any inconsistency causes the ABORT signal to assert,
and an abort symbol to be transmitted at the downstream
port. EDC fields are propagated through the chip core as
required to support the above described functionality. The
EDC field is not visible at the client ports.
The ABORT signal will also be asserted if an illegal address
or illegal sequence of symbols is detected. The symbol
which triggers ABORT assertion will contiue to move along
the ring until reaching its target node. This requires that the
ring be reset every time an abort is detected. The initial
occurrence of an abort is captured in the diagnostic register.
No subsequent abort will be logged (until the ring is reset).
Table 3.14 shows the matrix of data bits. An ‘‘X’’ indicates
the bits that are ‘‘Exclusive-ORed’’ to generate each partic-
ular check bit. Check bit 6 is generated by ‘‘Exclusive
ORing’’ all data and all check bits. CB
[
6:0
]
form the syn-
drome word.
Given a Single or Double bit error, the code has the follow-
ing properties:
1. If the syndrome word:
S
[
6:0
]
is zero (0),
then there is No
Error.
2. If any of the syndrome bits:
S
[
5:0
]
, is not zero (0), and
S6 is zero,
then there is a Double Error. The particular
bits in error can not be determined.
3. If any of the syndrome bits:
S
[
5:0
]
are not zero (0) and
S6 is one,
then there is a Single Error in either the data
or the check bits.
If a single bit in S
[
5:0
]
is one and S6 is one, then the corre-
sponding CB is in error and the data is correct.
If more than 1 bit in S
[
5:0
]
is set to one and S6 is one, then
the syndrome bits point to the data bit in error. See columns
of Table 3.14. S
[
5:0
]
pinpoints to the position number in the
mapping diagram at which bit is in error.
If all remaining bits, S
[
5:0
]
are zero and S6 is one, then CB6
is in error.
3.16 QR0001 EDC Errors and Client ‘‘Abort’’ Pin Func-
tionality
A bug has been identified in the abort operation. The
QR0001 ABORT signal does not match the intended opera-
tion as mentioned above. The intended operation is that the
following events will cause the ABORT pin to be asserted
and generate an abort symbol that will propagate around
TABLE 3.14. Error Detection Matrix
35-Bit Data Word
CHECK 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BITS
CB0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
X X
CB1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
X X
X
CB2
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X
X X X
CB3
X
X
X
X
X
X
X
X
X
X
X
X X X X X X
CB4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CB5
X
X
X
X
X
X
X
X
X
CB6
Exclusive ‘‘OR’’ All Data Bits (1–35) and All Check Bits (0–5)
C6 Aids in DED. Double Error Detection.
17
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