參數(shù)資料
型號(hào)： QR0001
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 440K
代理商： QR0001
5.0 Clock Signals
(Continued)
T
COtoTxCmin
k
T
TxMETA
k
T
COtoTxCmax
TL/F/11928–33
T
COtoRxCmin
k
T
RxMETA
k
T
COtoRxCmax
TL/F/11928–34
In general, the only way to guarantee that TxCLK and
RxCLK never violate the metastability window is to (1) de-
rive TxCLK and RxCLK from CKOUT or from the same
source from which CKOUT is derived, and (2) fix the delay
of TxCLK and RxCLK safely outside the window.
TL/F/11928–35
Design your circuit so as to avoid the danger window. The
size and position of this window is as specified in the follow-
ing table:
T
META
(ns)
Min
Max
Width
T
COtoTxC
b
11
b
7
4
T
COtoRxC
b
1
3
4
Why Falling Edges Blocks within the QR0001 device oper-
ate using two-phase logic. In general, half of the internal
latches are transparent during the clock-high time, and the
other half are transparent during clock-low time. It just so
happens that all of the latches involved in this bug are trans-
parent during clock-high time. The bug represents a failure
to decisively resolve a logic value to be true or false as
those latches closeDon the falling edges of their respective
clocks.
What about frequency and duty cycle The window of me-
tastability is fixed by chip-internal combinatorial delay paths,
whose values are independent of the clock frequency and
duty cycle.
What are the symptoms It would be extremely rare for any
single symbol to be corrupted. However the symbol stream
will be corrupted, as individual symbols or groups of sym-
bols may be randomly dropped or duplicated.
What circuits do I need If you are deriving RxCLK and
TxCLK from a buffered version of CKOUT, you are probably
already safe. Just analyze your own circuit to make sure that
TxCLK and RxCLK fall outside the danger window.
Multiple Clock Sources to Reduce Ring Jitter on
QR0001
Testing shows rings with more than 4 nodes accumulate
excessive jitter on the ring clock, which inhibits maximum
frequency operation. One method to stop jitter accumula-
tion, and improve frequency performance, on large rings is
to provide multiple clocks sources. Using several nodes on
all nodes as clock sources reduces accumulated ring jitter.
Using multiple clock sources, however, does increase ring
latency; the next QuickRing device (QR1001) is being de-
signed so that only one clock source will be required.
A 10 node ring was tested using 3 clock sources. It allowed
the ring to operate at full speed (33 MHz). To make a node a
clock source, the ‘‘CKSRC’’ input pin should be asserted,
and the clock should be connected to the ‘‘RGCLK’’ pin.
Note that all ‘‘RGCLK’’ pins in the Ring (Clock Source
Nodes) MUST be exactly the same frequency, however,
phase relationship is not an issue. This necessitates one
master clock source distributed to each QuickRing Clock
Source node, figure below. ‘‘CKSRC’’ asserted activates the
elasticity buffer at the Upstream port. This buffer adds 3
clock cycles delay to every symbol that arrives at the port,
including vouchers and tickets.
Multiple Clock Source Nodes
TL/F/11928–36
6.0 ABORT Signal
The ABORT signal is an output of the QR0001. Any one of
the following events can cause the ABORT signal to be
asserted:
D EDC error. Although ABORT signal pin is asserted, ring
abort
symbol
may
not
QuickRing.
propagate
around
entire
D Illegal sequence detected on the QuickRing (Refer to
following ring interface sections.) Ring abort symbol
propagates around QuickRing.
D Node ID detected greater than maximum number of
nodes in the ring. Ring abort symbol propagates around
QuickRing.
D Received an Abort symbol from the upstream port.
24
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PDF描述
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