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| 型號： | QR0001 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大小： | 440K |
| 代理商： | QR0001 |
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10.0 QR0001 Operation Flow
(Continued)
QR0001 sends an additional voucher as soon as it identifies
that one packet is not going to be enough to transmit all the
data in the transmit pipeline.
No packet is sent until a ticket is received. This includes low
bandwidth packets.
QR0001 does not wait for data; therefore, packets could
vary in size.
The largest and most efficient packet is one formed by 1
head symbol and 20 payload symbols, 21 symbols in all.
Low Bandwidth packets are 1 head and 1 payload symbol.
The client interface must stop writing data at the transmit
port within 20 non-null symbols after TxOK negates. The
count is reset if TxOK asserts again.
10.4 Inside the Target Node
At the target node, if the receiving controller has space for
one packet in the Target FIFO, it will send a ticket immedi-
ately to the source node in response to a voucher. A
QR0001 Target FIFO has space for 3 normal packets and 6
low bandwidth packets; therefore, the controller can have
only 3 outstanding normal tickets and 6 outstanding low
bandwidth tickets. If all tickets have been given, the receiv-
ing QR0001 will queue incoming vouchers in one of two
special buffers, called Target Handler and LB Target Han-
dler. The Target Handler can store 30 vouchers and the LB
Target Handler can store 10 vouchers for low bandwidth
transmission.
At the target node, a new ticket is released as soon as a
packet has exited the Target FIFO to the Rx Resynchroniz-
er. This is determined internally by matching the tickets giv-
en and the tails exiting the target FIFO.
If the target node cannot return a ticket or store the voucher
to be handled later, it will return a voucher rejected to the
source node. (The Source will sink the voucher and the
node will then re-send the voucher after 100 clock cycles.)
10.5 Summary of Target Node Actions
The target FIFO can handle 3 normal packets and 6 low
bandwidth packets. Therefore, only 3 normal tickets and 6
LB tickets can be outstanding at one time.
QR0001 can store 30 normal vouchers and 10 LB vouchers
before returning a voucherDreject to the source node.
The Head Stripper will remove the head of all packets be-
fore entering the Target FIFO, unless there is a change in
stream (new head).
Data may arrive at the Rx Port on every tick of the clock
unless the client stops the flow through the RxSTALL input.
RxET can be used to monitor the kind of data entering the
receive pipeline up to 20 symbols before it appears at the
receive port. When the Rx pipeline is free flowing in the
unblocked pipe (RxSTALL is negated), RxET will indicate
the Type:
1. Three clock cycles early the symbols (RxS) in the pipe-
lined timing and
2. Two clock cycles early the symbols (RxS) in the non-
pipelined timing.
11.0 Board Considerations
11.1 Upstream Port Signal Termination
The ring interface upstream port signals: UpSS
[
5:0
]
, and
UpCLK need external termination. The termination should
be a 100
X
resistor between the differential signal pair. The
resistor should be placed as close to the upstream port pins
as possible. Minimum parasitic inductance and capacitance
is desirable. Surface mount chip resistors with
g
1% toler-
ance are recommended. See Figure 11.1.
11.2 QuickRing Physical Layer Details
The QuickRing 180 MHz data signals dictate special care
for the physical layer design and layout. The use of LVDS
(Low Voltage Differential Signals) enables the very high fre-
quency operation. The LVDS also eases design because
the differential signals are forgiving to certain impedance
discontinuities in the signal path. If the discontinuities are at
the same electrical distance and have the same magnitude,
they will not distort the differential signal. Each single ended
signal may appear to have reflections, but if the differential
pair has the same minor reflections, then the differential
signal will not be affected. The skew between the pairs and
inside the pairs is a critical design criteria. These are the
basic guidelines for transporting the ring signals.
The skew between pairs and between single ended signals
inside a pair is critical. First, the skew between signal pairs.
The 350 MBaud signals only provide a bit width of about
TL/F/11928–26
FIGURE 11.1. Termination between the Differential Signal pair
27
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