參數(shù)資料
型號(hào)： QR0001
文件頁(yè)數(shù)： 3/40頁(yè)
文件大小： 440K
代理商： QR0001
1.0 Signal Description
Pin Name
I/O
No.
Description
RESET
I
1
RESET:
When this input is released, the initialization sequence begins.
ABORT
O
1
ABORT:
When asserted, it indicates that a failure was detected. ABORT is negated by asserting Reset.
PIPE
I
1
PIPE:
When PIPE is negated (non-pipelined timing), at the Client ports, both the symbol and type fields
correspond to each other during the same clock cycle. When PIPE is asserted (pipelined timing), the
timing of the Type field leads by one clock at the receive port and trails by one clock at the transmit port.
(The type and symbol fields are pipelined.)
NODE0
I
1
NODE0:
When asserted, the controller is configured as having Node ID 0. Node 0 is responsible for
governing the initialization process in the ring.
RGCLK
I
1
RING CLOCK:
This clock input is the time-base for the ring interface. A clock input should be present
when the CKSRC pin is asserted. When CKSRC is negated, RGCLK should be tied low.
CKSRC
I
1
CLOCK SOURCE:
Designates the source of the ring clock. When asserted, RGCLK is the clock source
used for the Ring interface. When this pin is negated, the clock is derived from the differential UpCLK.
CLKOUT
O
1
CLOCK OUT:
If CKSRC is asserted, then CLKOUT is frequency-locked to the RGCLK. If CKSRC is
negated, then CLKOUT is frequency-locked to the UpCLK.
UpCLK
I
2
UPSTREAM CLOCK:
This LVDS input clock comes from the neighbor upstream node and drives the
ring interface when CKSRC is negated.
UpSS
[
5:0
]
I
12
UPSTREAM SUB-SYMBOL:
These 6 LVDS inputs for the Ring interface carry the divided 42-bit symbol
from the downstream port of the previous node.
DnCLK
O
2
DOWNSTREAM CLOCK:
This LVDS output clock signal is derived from the clock that drives the Ring
interface. The transitions on the DnSS are in phase with transitions on the DnCLK signal.
DnSS
[
5:0
]
O
12
DOWNSTREAM SUB-SYMBOL:
These 6 LVDS outputs for the Ring interface carry the divided 42-bit
symbol for the upstream port of the next node.
TxCLK
I
1
TRANSMIT CLOCK:
On the Client interface, all transmit port signals are synchronous to the rising edge
of this clock.
TxT
[
1:0
]
I
2
TRANSMIT TYPE:
On the Client interface, this field defines (as head, data, frame or null) the contents
of TxS:
in the previous clock cycle when PIPE is asserted, plpelined timing.
in the current clock cycle when PIPE is negated, non-plpelined timing.
TxS
[
31:01
]
I
32
TRANSMIT SYMBOL:
On the Client interface, these signals form the data path of the transmit port.
TxOK
O
1
TRANSMIT OKAY:
On the Client interface, this is the transmit port status signal. It tells the client
whether or not another non-null symbol can be accepted. Loading of non-null symbols must cease
within 20 symbols of the negation of TxOK. Transmission may not resume until TxOK is reasserted.
RxCLK
I
1
RECEIVE CLOCK:
On the Client interface, all receive port signals are synchronous to the rising edge of
this clock. Except RxSTALL, which is sampled on the following edge of RxCLK.
RxT
[
1:0
]
O
2
RECEIVE TYPE:
On the Client interface, this field defines (as head, data, frame or null) the contents of
RxS:
in the next clock cycle for when PIPE is asserted, pipelined timing.
in the current clock cycle when PIPE is negated, non-pipelined timing.
RxS
[
31:0
]
O
32
RECEIVE SYMBOL:
On the Client interface, these signals form the data path of the receive port.
3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
QR0610T30 制造商:POWEREX 制造商全稱:Powerex Power Semiconductors 功能描述:Fast Recovery Diode Module (100 Amp/600 Volts)
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QR06A-2/106349 功能描述:BLWR CROSS FLOW 460X158MM 115VAC RoHS:是 類別:風(fēng)扇，熱管理 >> 風(fēng)扇 - AC 系列:QR06 其它有關(guān)文件:Declaration of Conformity 標(biāo)準(zhǔn)包裝:1 系列:- 氣流:- 軸承類型:- 風(fēng)扇類型:- 特點(diǎn):- 雜訊:- 功率（瓦特）:- RPM:- 尺寸/尺寸:- 靜態(tài)壓力:- 端子:- 電壓 - 額定:- 重量:- 額定電流:- 預(yù)期壽命:- 工作溫度:- 電壓范圍:- 其它名稱:Q5464961
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