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參數(shù)資料
| 型號： | QR0001 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大小： | 440K |
| 代理商： | QR0001 |
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11.0 Board Considerations
(Continued)
2.86 ns. The QuickRing UpPort needs 2.36 ns of this bit
width (including transitions) to successfully sample the val-
ue for each sub-symbol. This allows for a total skew budget
of 0.5 ns. The interconnect between DnPort and UpPort
should be limited to 350 ps. This provides 150 ps skew mar-
gin. The 350 ps can be divided between PCB traces, con-
nectors, headers, cables and all other media used in the
signal path.
The skew within a pair needs to be controlled because of
the EMI considerations. The simultaneous and opposite
transitions on paths within a pair create equal and opposing
electromagnetic fields. These EMF, the source of EMI,
serve to cancel each other thereby reducing EMI. The skew
within a pair should be controlled so that the single ended
EMF remain temporally and spatially relevant for the cancel-
ing affect.
The length of node interconnects is not critical to the opera-
tion of QuickRing until it degrades signal integrity. Nodes in
a ring can have different length interconnects. The maxi-
mum length of the interconnect depends on two qualities of
the interconnect; transition time degradation and amplitude
antenuation. Any extension in transition time due to the high
frequency filter affect of the interconnect, takes away from
the skew budget. The trade offs between the skew and tran-
sition time degradation must be balanced to allow for the
correct amount of sample time for the UpPort.
The signal attenuation affects the differential signal ampli-
tude at the receiver input. The receiver requires a differen-
tial voltage of at least 100 mV to guarantee a state. The
receiver actually is more sensitive than that under typical
operating conditions, but due to power supply and tempera-
ture variations, and test limitations, this is the data sheet
specification. As long as the differential voltage is guaran-
teed to be at least 150 mV and all the skew budget specifi-
cations are met, the receiver will operate correctly with ade-
quate noise margin.
12.0 Power and Decoupling Issues
12.1 Power Issues
The QR0001 device internally has Four distinct Power re-
gions. These regions are labeled (Refer to Figure 12.3):
1. Logic Power Pins
(V
CC
4,5,12,13; GND 3,15,18,19,28,29);
2. Client Receive Port Output Power Pins
(V
CC
6,7,8,9,10,11; GND 20,21,22,23,24,25,26,27);
3. LVDS Power Pins
(V
CC
1,3; GND 1,2,4,5,6,7,8,10,11,12,13,14,16,17);
4. PLL and Delay Element Power Pins
(V
CC
2; GND 9);.
It is currently recommended that the PC Board have sepa-
rate GND and V
CC
planes. Also, Power Region 2 should
have some additional isolation from the power plane. Com-
plete isolation is not required. The isolation aids in limiting
the Receive Port current spikes to the remaining plane. Re-
fer to Figure 12.1.
12.2 Decoupling Issues
lt is currently recommended that capacitors be placed local-
ly on all four corners of the device to provide an even filter-
ing. Capacitors should also be placed close to power region
2 to provide additional noise filtering. Refer to Figure 12.1.
Two capacitors should be placed in parallel to get high and
low frequency filtering along each side. However, each ca-
pacitor should have a via directiy to the V
CC
and Ground
planes.
For power region 4 (PLL and Delay Element Power Pin), two
decoupling capacitors should be placed as close to the pins
as possible (between V
CC2
and GND9). A trace from the pin
directly to the capacitors is recommended and separate
vias to ground plane for each capacitor. Refer to Figure
12.1.
TL/F/11928–28
FIGURE 12.1. QR0001 Power Region Isolation
28
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