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參數(shù)資料
| 型號： | QR0001 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 440K |
| 代理商： | QR0001 |
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5.0 Clock Signals
There are four clock domains in QuickRing, one for each
port. The transmit and receive ports are clocked by TxCLK
and RxCLK, respectively. The QR0001 core logic is clocked
either from RGCLK when CKSRC is asserted or from
UpCLK when CKSRC is negated. The upstream port is al-
ways clocked by UpCLK. Each controller derives the DnCLK
from the clock that drives the downstream port.
TABLE 5.1. Clock Signal
QR0001 Interface
CKSRC
Clock Source
DnCLK,
H
RGCLK
CLKOUT
L
UpCLK
The client ports are asynchronous from each other. The
Upstream and Downstream ports are synchronous with
each other when CKSRC is negated, and frequency locked,
not phase locked, when CKSRC is asserted.
For all clocks, the minimum period is 20 ns having maximum
frequency of 50 MHz.
TIMING SYNCHRONIZATION
On QR0001, the RGCLK, TxCLK and RxCLK must be syn-
chronized. Two methods for synchronization are shown be-
low.
TL/F/11928–30
FIGURE 5.1. Recommended for Card-to-Card Connections Over QuickRing
#
RGCLK on the CKSRC node is driven by the local host clock that drives RxCLK and TxCLK.
TL/F/11928–31
FIGURE 5.2. Recommended for Box-to-Box or Card-to-Card Connectors Over QuickRing
#
CLKOUT is used on all other nodes to drive RxCLK, TxCLK, and therefore the HOST SYSTEM CLOCK.
#
Note that CLKOUT is not intended to drive large loads and can only sink a few mA. If the application requires the ability to
drive other system clocks then add a buffer.
QR0001 Resynchronizer Issue
The core of QR0001 operates in the timing domain of the
ring in which it is connected. The intent of the QR0001 de-
sign is to allow the timing domain of the client interface to
be independent of the ring clock domain. Unfortunately,
there is a bug in the first release of QR0001 that affects
both the transmit and receive resynchronizers whose task is
to decouple the clock domains from each other. These cir-
cuits fail in such a way that data may be erroneously repli-
cated or deleted as it crosses between the ring clock do-
main and the client clock domains. The failure occurs be-
cause of metastable states in the logic that controls these
resynchronizer blocks.
The transmit resynchronizer is susceptible to metastability
whenever the delay between CKOUT and TxCLK falls within
a range which we can call the window of metastability or the
danger window.
Likewise, the receive resynchronizer may experience me-
tastability and data stream corruption if the delay of RxCLK
from CKOUT falls within its window of metastability.
The following two inequalities identify the window of metast-
ability, within which metastability and data stream corruption
is possible.
23
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