參數(shù)資料
型號(hào)： RK80530KZ017512
英文描述： MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷
文件頁(yè)數(shù)： 34/86頁(yè)
文件大小： 882K
代理商： RK80530KZ017512
34
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
NOTE:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. These specifications are tested during manufacturing.
3. All timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.9 V at the processor pins.
All APIC I/O signal timings are referenced at 1.0 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
load pulled up to 1.5 V.
Table 18. System Bus Timing Specifications (Reset Conditions)
1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time
4
BCLKs
13
Before deassertion
of RESET#
After clock that
deasserts RESET#
2
20
BCLKs
13
Table 19. System Bus Timing Specifications (APIC Clock and APIC I/O)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T21: PICCLK Frequency
T22: PICCLK Period
T23: PICCLK High Time
T24: PICCLK Low Time
T25: PICCLK Rise Time
T26: PICCLK Fall Time
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
2.0
30.0
10.5
10.5
0.25
0.25
8.0
2.5
1.5
1.5
33.3
500.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
10
12
12
11
10
@ > 1.60V
@ < 0.40V
(0.40V - 1.60V)
(1.60 - 0.40V)
4
4
4, 5, 6
4, 5, 6
3.0
3.0
8.7
12.0
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