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參數(shù)資料
| 型號： | RK80530KZ017512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 79/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ017512 |
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Datasheet
79
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
CPUPRES#
O
The CPUPRES# signal is defined to allow a system design to detect the presence
of a terminator device or processor in a PGA370 socket. Combined with the VID
combination of VID[25mV,3:0]= 11111 (see
Section 2.6
), a system can determine if
a socket is occupied, and whether a processor core is present. See the table below
for states and values for determining the presence of a device.
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEP[7:0]#
I/O
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DETECT
O
A tri-state (high-impedance) output. Can be used for platforms that need to
differentiate Intel Pentium III processors with 512KB L2 Cache that support
VTT=1.25V only, from Pentium
III processors (AF36=VSS) that support
VTT=1.50V only. The output on this signal is stable when VTT is stable. Please
refer to the appropriate Platform Design Guide for implementation details.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
DYN_OE
I
The DYN_OE allows the BSEL and VID signals to be driven out from the processor.
When this signal is low (a condition that will occur if the Intel Pentium III
processor is installed in a non-supported platform), the VID and BSEL signals will
be tri-stated and the platform pull-up resistors will set the VID and BSEL to all ‘1’s’
which is a safe setting. This signal must be connected to a 1k
resistor to V
.
Refer to the platform design guide for implementation detail and resistor tolerance.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
Table 39. Signal Description (Sheet 4 of 9)
Name
Type
Description
PGA370 Socket Occupation Truth Table
Signal
Value
Status
CPUPRES#
VID[25mV,3:0]
0
Anything other
than ‘11111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[25mV,3:0]
0
11111
Terminator device installed in the
PGA370 socket (i.e., no core present).
CPUPRES#
VID[25mV,3:0]
1
Any value
PGA370 socket not occupied.
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