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參數(shù)資料
| 型號(hào)： | RK80530KZ017512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 35/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ017512 |
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Datasheet
35
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. All timings for the TAP signals are referenced to the TCK rising edge at 1.0 V at the processor pins. All TAP
signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Table 20. System Bus Timing Specifications (TAP Connection)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T30: TCK Frequency
16.667
MHz
T31: TCK Period
60.0
ns
10
T32: TCK High Time
25.0
ns
10
Vcmos_ref +
0.200V,
10
T33: TCK Low Time
25.0
ns
10
10
T34: TCK Rise Time
5.0
ns
10
(Vcmos_ref -
0.200V) -
(Vcmos_ref +
0.200V),
4, 10
T35: TCK Fall Time
5.0
ns
10
(Vcmos_ref +
0.200V) -
(Vcmos_ref -
0.200V),
4, 10
T36: TRST# Pulse Width
40.0
ns
17
Asynchronous,
10
T37: TDI, TMS Setup Time
5.0
ns
16
5
T38: TDI, TMS Hold Time
14.0
ns
16
5
T39: TDO Valid Delay
1.0
10.0
ns
16
6, 7
T40: TDO Float Delay
25.0
ns
16
6, 7, 10
T41: All Non-Test Outputs Valid Delay
2.0
25.0
ns
16
6, 8, 9
T42: All Non-Test Inputs Setup Time
25.0
ns
16
6, 8, 9, 10
T43: All Non-Test Inputs Setup Time
5.0
ns
16
5, 8, 9
T44: All Non-Test Inputs Hold Time
13.0
ns
16
5, 8, 9
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