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參數(shù)資料
| 型號(hào)： | RK80530KZ017512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 78/86頁 |
| 文件大小： | 882K |
| 代理商： | RK80530KZ017512 |
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78
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
BR0#/BR1#
I/O
The BR0# and BR1#(Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
During power-up configuration, the central agent asserts the BR0# bus signal in the
system to assign the symmetric agent ID to the processor. The processor samples
its BR0# pin on the active-to-inactive transition of the RESET# to obtain its
symmetric agent ID. The processor asserts the BR0# pin to request the system
bus. All agents then configure their pins to match the appropriate bus signal
protocol, as shown below.
For uni-processor designs, BR0# must be connected to a 10-56
resistor to V
.
Refer to the platform design guide for implementation detail and resistor tolerance.
BSEL[1:0]
O
The BSEL signals are CMOS signals which are used to select the system bus
frequency. A BSEL[1:0] = ‘11’ selects a 133 MHz system bus frequency. The
frequency is determined by the processor(s), chipset, and frequency synthesizer
capabilities. All system bus agents must operate at the same frequency. The Intel
Pentium III processor with 512KB L2 Cache operates at 133 MHz system bus
frequency.
These signals must be pulled up to 3.3V power rail with 330 - 1 K
resistors and
provided as a frequency selection signal to the clock driver/synthesizer and chipset.
Refer to the platform design guide for implementation detail and resistor tolerance.
CLKREF
I
In Single-ended clock mode the CLKREF input is a filtered 1.25V supply voltage for
the processor PLL. A voltage divider and decoupling solution is provided by the
motherboard. See the design guide for implementation details.
When the processor operates in differential clock mode, this signal becomes
BCLK#.
Table 39. Signal Description (Sheet 3 of 9)
Name
Type
Description
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
BR0# (I/O) and BR1# Signals Rotating Interconnect
Pin Sampled Active in RESET#
Agent ID
BR0#
0
BR1#
3
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