- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373275 > RK80530KZ017512 MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC PDF資料下載
參數(shù)資料
| 型號(hào)： | RK80530KZ017512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 83/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ017512 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當(dāng)前第83頁第84頁第85頁第86頁
Datasheet
83
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
SMI#
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts while in
the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
THERMDN
O
Thermal Diode Cathode. Used to calculate core (junction) temperature. See
Section 4.1
.
THERMDP
I
Thermal Diode Anode. Used to calculate core (junction) temperature. See
Section
4.1
.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active or core power is
removed. There is no hysteresis built into the thermal sensor itself; as long as the
die temperature drops below the trip level, a RESET# pulse will reset the processor
and execution will continue. If the temperature has not dropped below the trip level,
the processor will continue to drive THERMTRIP# and remain stopped.
In the event the processor drives the THERMTRIP# signal active during valid
operation, both the Vcc and Vtt supplies to the processor must be turned off to
prevent thermal runaway of the processor. Valid operation refers to the operating
conditions where the THERMTRIP# signal is guaranteed valid. The time required
from THERMTRIP# asserted to Vcc rail at 1/2 nominal is 5 seconds and
THERMTRIP# asserted to Vtt rail at 1/2 nominal is 5 seconds. Once Vcc and Vtt
supplies are turned off the THERMTRIP# signal will be deactivated. System logic
should ensure no “unsafe” power cycling occurs due to this deassertion.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY#
I/O
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
V
CMOS_REF
I
The V
CMOS_REF
input pin supplies non-AGTL reference voltage, which is typically 2/
3 of V
is used by the non-AGTL receivers to determine if a signal
is a logical 0 or a logical 1.
Table 39. Signal Description (Sheet 8 of 9)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RK80532PC041512 | Microprocessor |
| RK9410 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO |
| RKC-SERIES | Interface IC |
| RKCB-SERIES | Interface IC |
| RKCR-SERIES | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RK80530KZ017512S L5XL | 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G |
| RK80530KZ017512S L6BY | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.4GHz 370-Pin FCPGA2 |
| RK80530PZ001256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| RK80530PZ006256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| RK80530PZ009256 | 制造商:Rochester Electronics LLC 功能描述:PIII 1.2G 256 ON DIE CACHE FC-PGA2 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。