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參數(shù)資料
| 型號： | rosa51 |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard Adapter(多媒體卡適配器) |
| 中文描述： | 多媒體卡（多媒體卡適配器） |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 510K |
| 代理商： | ROSA51 |
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Siemens AG Semiconductors
Version 5.2
Confidential
20/10/1998
17
This interface supports a software handshake for simple protocols. It can be extended to a hard-
ware handshake for every data word transfer. For some card interface macro commands with long
response times it will be useful to enable an interrupt. In this way the application does not need to
poll continuously the status of the last command.
A byte transfer on the adapter interface begins with the assertion of chip select (
&6B1
) and setting
of
&'
for command or data address. At the same time
5:
is set to indicate the transfer direction.
An actual transfer is started with the assertion of
67%B1
. For writes the byte on
'$7$
must be valid
while strobe is active. On reads
$&.B1
indicates a valid byte.
67%B1
deasserted marks the com-
pletion of a transfer.
The interface has basically only two addresses: a command and a data address. MultiMediaCard
system commands, as defined in chapter 5, must be written to the command address. Reading from
this address returns the current status of the adapter and not the system command last written. The
data address is for all other information, be it actual payload data or arguments to a system com-
mand. Each operation on the adapter interface begins with a command and is followed by zero or
more data bytes.
,QWHUUXSWV
The adapter contains four interrupt registers. The first is accessed by reading from the command
address. The others are read by sending a CAM and reading the data register afterwards.
Every defined error in the adapter or on a card may cause an interrupt request to the application.
Additionally, certain states, e.g. block transfer completed, can be indicated by an interrupt. All inter-
rupt sources can be masked individually. Servicing an interrupt should be started by reading the
command status register. A rough classification of the source is given there indicating which status
register should be read next. All interrupts are clear-by-read. The command status register contains
the status of ROSA.
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7\SH
'HVFULSWLRQ
7
R
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- ROSA controller active
A ‘1’ indicates that ROSA is working on the last command.
A ‘0’ indicates that ROSA is waiting for a new command.
3LSH)XOO
- command pipeline full
A ‘1’ indicates that the command pipeline is full. The command sent last was accepted
but cannot be processed yet, because ROSA is still working on the command issued one
before last.
'DW%XV\
-
'$7
line busy
A ‘1’ indicates that currently data is transferred across the MultiMediaCard
'$7
lines.
6
R
5
R
7DEOH&RPPDQGUHJLVWHU
)LJXUH5HJLVWHUPDS
CD
DATA[7:0]
DATA
COMMAND
0
1
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