參數(shù)資料
型號(hào)： rosa51
廠商： SIEMENS AG
英文描述： MultiMediaCard Adapter(多媒體卡適配器)
中文描述： 多媒體卡（多媒體卡適配器）
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 510K
代理商： ROSA51
526$
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Siemens AG Semiconductors
Version 5.2
Confidential
20/10/1998
26
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This unit (rosa_crc) is a generic CRC coder/decoder. It is customized for the
'$7
line CRC genera-
tion and verification. The
'$7
CRC is generated with and checked against the following polynomial:
CRC polynomial: G(x) = x
16
+ x
12
+ x
5
+ 1
M(x) = (first bit) * x
n-1
+...+ (last bit) * x
0
CRC[15...0] = Remainder [(M(x) * x
16
) / G(x)]
n is the number of CRC protected bits: for data blocks n = number of bits in the block.
For data blocks one CRC per block is generated/checked regardless of the number of
'$7
lines.
The
'$7
rosa_crc has a 8 bit parallel input either from the memory on writes or from the dat shift
register on reads. When mcif_datcrcen asserted a new CRC value is computed. It has a 16 bit par-
allel output port. The CRC verification compares this port with zero, indicating transferred data was
correct. The registers can be reset with mcif_datcrcreset_n.
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This process is a slave of the data path controller rosa_mc. It is included in rosa_if because it inter-
faces with the MultiMediaCard bus
'$7
lines and runs synchronous to MultiMediaCard bus clock.
An 8 bit shift register catches the information that is read/written on the DAT lines. A counter indi-
cates the fullness of the data_reg. Nibble and serial mode are implemented. Data comes from three
sources rosa_mc (mcif_data), DAT (dat_in) or rosa_crc (dat_crc_logic) selected by mcif_datrw.
cmd_out
O
This signal is connected to the MultiMediaCard bus
&0'
line when
cmd_rw_out is low.
This signal indicates the direction of the current
&0'
line transfer.
‘1’ - read,
‘0’ - write (default).
cmd_rw_out
O
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H
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7DEOH&0'OLQHFRQWUROOHULQWHUIDFH
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data in
data delay
C
=
data out
good
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