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參數(shù)資料
| 型號(hào)： | rosa51 |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard Adapter(多媒體卡適配器) |
| 中文描述： | 多媒體卡（多媒體卡適配器） |
| 文件頁數(shù)： | 18/54頁 |
| 文件大?。?/td> | 510K |
| 代理商： | ROSA51 |
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Siemens AG Semiconductors
Version 5.2
Confidential
20/10/1998
18
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If data buffering is required ROSA is configured to include a memory interface. The following table
defines the memory interface of the adapter.
4
RC
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- data FIFO full
After the command register is read by the application this bit is cleared internally.
In case of concurrent accesses to this bit, it remains ‘1’.
A ‘1’ indicates that the FIFO is full .
Default value is ‘0’ (not full).
)LIR(PSW\
- data FIFO empty
After the command register is read by the application this bit is cleared internally.
In case of concurrent accesses to this bit, it remains ‘1’.
A ‘1’ indicates that the FIFO is empty.
Default value is ‘1’ (empty).
,UT$GD
- Adapter interrupt request
After the command register is read by the application this bit is cleared internally.
In case of concurrent accesses to this bit, it remains ‘1’.
A ‘1’ indicates that a MultiMediaCard bus interrupt or protocol error occured. The register
is defined in chapter 6.2 table 19.
Default value is ‘0’ (no interrupt).
,UT&LP
- Macro interrupt request
After the command register is read by the application this bit is cleared internally.
In case of concurrent accesses to this bit, it remains ‘1’.
A ‘1’ indicates that internal interrupt sources requested an interrupt. The register is
defined in chapter 6.2 table 18.
Default value is ‘0’ (no interrupt).
,UT&DUG
- Card interrupt request
After the command register is read by the application this bit is cleared internally.
In case of concurrent accesses to this bit, it remains ‘1’.
A ‘1’ indicates that one of the MultiMediaCard status interrupt sources requested an inter-
rupt. The register is defined in chapter 6.2 table 17.
Default value is ‘0’ (no interrupt).
3
RC
2
RC
1
RC
0
RC
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1)Direction and mode: I - input; O - output; 3-state driver
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RAM_ADDR
RAM_RD_DATA[
7:0]
RAM_WR_DATA[
7:0]
RAM_WR_EN
O
I
memory address, the width can be configured between 9 to 16 bits.
read (down link) data from memory
O (3-
state)
O
write (up link) data to memory
write enable, active high, toggles on positive edge of clock
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