- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376314 > rosa51 (SIEMENS AG) MultiMediaCard Adapter(多媒體卡適配器) PDF資料下載
參數(shù)資料
| 型號： | rosa51 |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard Adapter(多媒體卡適配器) |
| 中文描述： | 多媒體卡（多媒體卡適配器） |
| 文件頁數(shù)： | 27/54頁 |
| 文件大?。?/td> | 510K |
| 代理商： | ROSA51 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
526$
$UFKLWHFWXUH
Siemens AG Semiconductors
Version 5.2
Confidential
20/10/1998
27
mcif_datset prepares everything for a new byte transfer, sets the counter and loads the data_reg.
&/.FRQWUROOHU
The clock controller process drives the MultiMediaCard bus
&/.
line.
This unit calculates the current MultiMediaCard clock period in units of ROSA system clock cycles.
First the parameters TRAN_SPEED and SW_FACTOR from the MultiMediaCard CSD register
define the maximum possible MultiMediaCard clock frequency. After that the ratio between ROSA
system clock and a 20 MHz clock influence the final period.
If the MultiMediaCard bus is powered up the MultiMediaCard clock may start. To get a symmetrical
clock waveform a counter is loaded with the calculated clock period. When it reaches period/2 the
clk_out goes low and when is reaches zero clk_out goes high. The clock generation can be
requested by rosa_rc, rosa_cmd and rosa_mc. Clock generation starts and ends only when clk_out
is low. rosa_mc can overrule the requests and stall the clock with mcif_clkstop. To avoid spikes on
clk_out the mcif_clkstop signal is latched up on the negative edge of clk.
If the maximum MultiMediaCard clock frequency is the same as the ROSA system clock frequency
then clk is directly connected to the MultiMediaCard bus
&/.
line. When implementing this special
case care must be taken to avoid spikes and clk line load balancing.
1DPH
7\S
H
'HVFULSWLRQ
mmcclk
rcif_dat_width
I
I
This signal causes a shift in the data register. It is active high.
This signal indicates how many
'$7
lines are active.
‘1’ - nibble mode = 4
'$7
lines,
‘0’ - serial mode = 1
'$7
line (default).
This signal forces the dat_out lines to high. It is active high.
This signal resets the bit counter and load the data register. It is active high.
These lines carry the direction of
'$7
and the source for the data register.
00b - write to MultiMediaCard bus and read data from rosa_mc into
data_reg.
01b - write to MultiMediaCard bus and read data from DATCRC MSByte
into data_reg
10b - write to MultiMediaCard bus and read data from DATCRC LSByte
into data_reg
11b - read from MultiMediaCard bus and write from data_reg to rosa_mc
These lines reflect the DATCRC register.
This bus is used to transfer data from memory to rosa_if.
This bus is used to transfer data from rosa_if to memory.
This bus reflects the data_reg bit counter = the number of bits transferred.
mcif_datpullup
mcif_datset
mcif_datrw[1:0]
I
I
I
dat_crc_logic[15:0]
mcif_data[7:0]
ifmc_data[7:0]
ifmc_dat_counter[2:0
]
dat_in[DatWidth-1:0]
dat_out[DatWidth-
1:0]
dat_rw_out
I
I
O
O
I
These signals are always connected to the MultiMediaCard bus
'$7
lines.
These signals are connected to the MultiMediaCard bus
'$7
lines when
dat_rw_out is low.
This signal indicates the direction of the current
'$7
lines transfer.
‘1’ - read,
‘0’ - write (default).
O
O
7DEOH00&'$7SURFHVVLQWHUIDFH
相關PDF資料 |
PDF描述 |
|---|---|
| ROSE-1 | FREQUENCY MIXERS |
| ROSE-2 | FREQUENCY MIXERS |
| ROSE-50 | SMB Termination |
| RP-12C | mask-diffused gaasp led |
| RP05-4824DE | POWERLINE - DC/DC - CONVERTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ROSE1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| ROSE-1 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:FREQUENCY MIXERS |
| ROSE2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| ROSE-2 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:FREQUENCY MIXERS |
| ROSE-50 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:SMB Termination |
發(fā)布緊急采購，3分鐘左右您將得到回復。