參數(shù)資料
型號(hào)： rosa51
廠商： SIEMENS AG
英文描述： MultiMediaCard Adapter(多媒體卡適配器)
中文描述： 多媒體卡（多媒體卡適配器）
文件頁(yè)數(shù)： 29/54頁(yè)
文件大?。?/td> 510K
代理商： ROSA51
526$
$UFKLWHFWXUH
Siemens AG Semiconductors
Version 5.2
Confidential
20/10/1998
29
The following figure depicts the architecture of the adapter interface.
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cs_n_in
I
This signal selects ROSA as the target of the next adapter interface trans-
actions. It is active low.
This signal indicates the beginning and end of a transaction. The assertion
declares cd_in and rw_in as valid and stable, on writes data_in too. It is
active low.
This signal is the address of the adapter interface selecting one of two pos-
sible registers.
‘1’ - control register,
‘0’ - data register.
This signal indicates the direction of the transaction.
‘1’ - read,
‘0’ - write.
These lines are directly connected to
'$7$
.
rosa_rc acknowledges a transfer request.
rosa_mc acknowledges a transfer request.
These signals define the destination and source registers for data running
across command_bus. It selects whether data is read from or written to
command_bus.
This bus is used to transfer data between rosa_ad and rosa_mc or rosa_rc.
This signal acknowledges the requested data transfer. It is active low.
This signal is the latched
67%B1
. It is active high.
This signal is the latched
&'
.
stb_n_in
I
cd_in
I
rw_in
I
data_in[7:0]
rcad_rdy_c
mcad_ack
rc_command_addr[]
I
I
I
I
command_bus[7:0]
ack_n_out
adrc_stb
adrc_cd
IO
O
O
O
7DEOH$GDSWHULQWHUIDFH
)LJXUH$GDSWHULQWHUIDFHEORFNGLDJUDP
CS_N
STB_N
RW
CD
ACK_N
IRQ_N
DATA[7:0]
Interrupt controller
rosa_irq
ack logic
adrc_stb
adrc_rw
adrc_cd
command_bus[7:0]
rcad_rdy_c
mcad_ack
RD_C
rosa_ad
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