參數(shù)資料
型號(hào)： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 14/72頁(yè)
文件大?。?/td> 360K
代理商： SAA6721E
1999 May 11
14
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
7.2.3
I
2
C-
BUS INTERFACE CLOCK
(SCL)
This clock drives the interface to the external
microcontroller. Its frequency range is from
100 kHz to 1 MHz.
7.2.4
S
YSTEM CLOCK
(CLK)
This clock is used to drive the internal PLL. The frequency
range is from 24 to 50 MHz.
7.2.5
TFT
PANEL CLOCK
(PCLK)
This clock is the timing reference for the panel.
The frequency is the same as the system clock, or it can
be generated from the internal PLL by using the following
formula:
Where N = pre-divider ratio and M = post-divider ratio.
7.3
RGB input port
The RGB input port can operate in two modes; single pixel
mode (24 bits) and double pixel mode (48 bits). For single
pixel mode only ports VPA7 to VPA0, VPB7 to VPB0, and
VPC7 to VPC0 are internally sampled. For double pixel
mode two pixels must be provided at the RGB input port.
f_tft
N
f_system
M
32
×
=
Therefore ports VPD7 to VPD0, VPE7 to VPE0, and
VPF7 to VPF0 are also needed.
The VPA/B/C ports are sampled on the rising edge of the
RGB input clock (VCLK), and the VPD/E/F ports on the
falling edge (see Fig.3).
The synchronization pulses from the graphics card are
used to identify the frame outline. The vertical
synchronization pulse is connected to pin VVS, and the
horizontal synchronization pulse is connected to pin VHS.
For calibrating the connected Analog-to-Digital Converter
(ADC) the SAA6721E delivers a clamp pulse at
pin CLAMP, and a gain correction pulse at pin GAINC
(see Fig.4).
The sample window of the RGB input port is controlled by
four counters; horizontal and vertical offset, and horizontal
and vertical window size.
The offset counters start at the inactive or second edge of
their corresponding synchronization signal.
Fig.3 RGB input port timing.
handbook, full pagewidth
VCLK
VPA/B/C
VPD/E/F
MHB243
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