參數(shù)資料
型號： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁數(shù)： 42/72頁
文件大?。?/td> 360K
代理商： SAA6721E
1999 May 11
42
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
G
ENERAL CONFIGURATION
2
Line length controlling in active video region
Line length controlling disabled
Line length controlling enabled
Line length controlling in border region
Line length controlling disabled
Line length controlling enabled
Line length controlling in top blanking region
Line length controlling disabled
Line length controlling enabled
Output interface mode
Free running output interface timing (external SDRAM required)
Synchronous output interface timing (without external SDRAM)
Blanking mode
Normal operating mode
All data outputs are at LOW level (black colour)
Output interface enabling
Output interface disabled, no data processing
Output interface enabled, normal data processing
Data qualifier generation mode
Disable pulse generation at pin PDE during vertical syncs
Enable pulse generation at pin PDE during vertical syncs
Line synchronization
Normal mode
Do not use
203
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
H
ORIZONTAL LINE LENGTH IN BLANKING REGION
Horizontal line length in blanking region
204 and 205
W
D10 to D0
H
ORIZONTAL LINE LENGTH IN BORDER REGION
Horizontal line length in border region
206 and 207
W
D10 to D0
H
ORIZONTAL LINE LENGTH IN ACTIVE VIDEO REGION
Horizontal line length in active video region
208 and 209
W
D10 to D0
V
ERTICAL FRAME END
Vertical frame length
210 and 211
W
D10 to D0
V
ERTICAL BORDER REGION START
Vertical start of border region
212 and 213
W
D10 to D0
V
ERTICAL ACTIVE VIDEO REGION START
Vertical start of active video region
214 and 215
W
D10 to D0
H
ORIZONTAL DELAY OF START OF VERTICAL SYNC
Horizontal start delay of vertical sync pulse at pin PVS
216 and 217
W
D10 to D0
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA6750 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE
SAA6750H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE
SAA6752HS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS/V103 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS/V103,557 功能描述:IC AUD/VID ENCODER MPEG 208-SQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
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