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參數(shù)資料
| 型號： | SAA6721E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 圖形處理器 |
| 英文描述： | SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎) |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 48/72頁 |
| 文件大?。?/td> | 360K |
| 代理商： | SAA6721E |
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1999 May 11
48
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
Fig.15 Line sampling.
handbook, full pagewidth
MHB255
odd line
even line
line number
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Vsync end
offset
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8.3.5.1
Field capturing
Another problem that must be considered is frame
dropping. It is possible that the connected video source
only provides either odd or even frames, or that the video
source drops frames. Therefore the input interface must
process the incoming video stream in several ways, as
shown in Table 12.
Table 12
Field capture modes
yuv_field_mode[1 and 0]
DESCRIPTION
0
all incoming frames are
captured
after an odd frame the next
even frame will be
captured, and vice versa
capture only odd frames
capture only even frames
1
2
3
8.3.5.2
YUV clocking
VCLK, or alternatively the clock from MCLKI, is used for
clocking the input interface in YUV mode and the data path
behind the external clock. This second port will be used if
yuv_clk_mux is set to logic 1. The external clock is the
line-locked video clock from the video decoder. This clock
is gated by CREF and applied at pin VPD7. Data is only to
be sampled if this signal is asserted. Alternatively the
line-locked video clock divided by two can be used
(if provided by the decoder). In this event CREF must be
tied to logic 1 or logic 0 depending on its programmed
polarity.
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| SAA6750H | Encoder for MPEG2 image recording EMPIRE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
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