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參數(shù)資料
| 型號(hào)： | SAA6721E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 圖形處理器 |
| 英文描述： | SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎) |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁(yè)數(shù)： | 19/72頁(yè) |
| 文件大小： | 360K |
| 代理商： | SAA6721E |
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1999 May 11
19
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
7.7
I
2
C-bus interface
This serial interface consists of only two signals, the serial
clock line (SCL) and the serial data line (SDA).
The maximum supported frequency on this bus is 1 MHz.
Spikes with a maximum pulse length of 50 ns are
suppressed by the internal input filter.
The SAA6721E operates as a slave and cannot initiate
any data transfer, so the clock line is always input. Via the
data line, data is transmitted and received, so this pin must
be input/output. The SCL and SDA lines are driven by
open-drain stages and pull-up resistors. When a logic 0 is
applied, the bus is set to ground level via the output
buffers. When a logic 1 is applied, the output buffer
switches to 3-state and the pull-up resistors pull the bus up
to +5 V.
Data transfer changes on SDA are allowed only when SCL
is LOW. Data is sampled on the positive edge of SCL.
In Idle state the output buffers are in 3-state, and the bus
is HIGH. A data transfer must be initiated by an I
2
C-bus
master device. This is done by sending a START condition
when SDA changes from HIGH to LOW when SCL is HIGH
(see Fig.8).
The device address of the SAA6721E must then be sent
with the desired I/O direction.
If the SAA6721E reads its device address, it
acknowledges this by sending a single bit ACK to the
master. If write mode was selected, the master sends the
register address to be written and then the data bytes.
If read mode was selected, the SAA6721E sends the data
bytes starting from the last address accessed either by
write command or the next address at a read command.
All byte transfers are acknowledged from the receiving
device. The data transfer is aborted by sending a STOP
condition, when SDA changes from LOW to HIGH when
SCL is HIGH (see Fig.9).
If a new address has to be read or written, it is possible to
send a new START condition without a preceding STOP
condition. In this case the bus is still occupied by the
master, and it can initiate a new data transfer. This is
useful for read activities, where at first the register address
must be sent in write mode and after that a read command
will be sent to read data from this and following addresses.
Fig.8 Start of a data transfer.
handbook, full pagewidth
MHB248
SDA
A4
A1
A2
A3
A6
A5
ACK
R/W
A0
R5
R7
R6
START condition
acknowledge
Fig.9 End of a data transfer.
handbook, full pagewidth
MHB249
SDA
D7
D4
D5
D6
D1
D0
ACK
D2
D3
A/A
D1
D0
STOP condition
acknowledge/
not acknowledge
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
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