參數(shù)資料
型號(hào): SAA6721E
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 圖形處理器
英文描述: SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述: GRAPHICS PROCESSOR, PBGA292
封裝: 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù): 22/72頁(yè)
文件大?。?/td> 360K
代理商: SAA6721E
1999 May 11
22
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
19
R
black_
pixels[8]
20
21
22
23
R
R
R
R
non_black_lines[7 to 0]
non_black_lines[10 to 8]
non_black_pixels[7 to 0]
non_black_pixels[11 to 8]
General configuration
24
W
intr_clear
single_
adc_mode
no_
memory_
mode
yuv_clk_
mux
memory_
init
reset_
input_path
reset_
memory_
path
blank_
screen
reset_
proc_path
25
W
csm_
bypass
frc_on
power_
down
Clock distribution
26
W
por_mclk
pre_div_
enable
post_div_
enable
pre_div_
half_clock
post_div_
half_clock
pre_div_clock_p_low[3 to 0]
pre_div_clock_n_low[3 to 0]
pre_div_clock_n_offs[3 to 0]
post_div_clock_p_low[3 to 0]
post_div_clock_n_low[3 to 0]
post_div_clock_n_offs[3 to 0]
pll_enable
pll_pclk
pll_mclk
27
28
29
30
31
32
W
W
W
W
W
W
pre_div_clock_p_high[3 to 0]
pre_div_clock_n_high[3 to 0]
post_div_clock_p_high[3 to 0]
post_div_clock_n_high[3 to 0]
Input interface
33
W
rgb_interl_
on
in_form_
on
rgb_proc_
on
adc_
sample_
seq
gainc_pol
clamp_pol
vs_pol
hs_pol
34
W
field_
reverse
yuv_field_mode
[1 and 0]
yuv_input_mode
[1 and 0]
yuv_href_
pol
yuv_cref_
pol
35
36
37
38
39
40
41
42
43
44
45
46
W
W
W
W
W
W
W
W
W
W
W
W
v_offset[7 to 0]
v_offset[10 to 8]
h_offset[7 to 0]
h_offset[11 to 8]
v_length[7 to 0]
v_length[10 to 8]
h_length[7 to 0]
h_length[11 to 8]
clamp_on[7 to 0]
clamp_off[7 to 0]
gainc_on_delay[7 to 0]
gainc_off_delay[7 to 0]
ADDRESS R/W
D7
D6
D5
D4
D3
D2
D1
D0
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