參數(shù)資料
型號(hào)： SC16IS741IPW
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述： 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝： 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁(yè)數(shù)： 10/52頁(yè)
文件大?。?/td> 382K
代理商： SC16IS741IPW
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
10 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.4 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 4
.
Table 4
summarizes the state of register.
Table 4.
Register
Interrupt Enable Register
[1]
Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR or Software Reset, that is, they hold their initialization values during reset.
Table 5
summarizes the state of registers after reset.
Table 5.
Signal
TX
RTS
IRQ
Register reset
[1]
Reset state
all bits cleared
Interrupt Identification Register
FIFO Control Register
bit 0 is set; all other bits cleared
all bits cleared
Line Control Register
Modem Control Register
reset to 0001 1101 (0x1D)
all bits cleared
Line Status Register
Modem Status Register
bit 5 and bit 6 set; all other bits cleared
bits 0:3 cleared; bits 4:7 input signals
Enhanced Feature Register
Receiver Holding Register
all bits cleared
pointer logic cleared
Transmitter Holding Register
pointer logic cleared
Transmission Control Register
Trigger Level Register
all bits cleared.
all bits cleared.
Transmit FIFO level
reset to 0100 0000 (0x40)
Receive FIFO level
all bits cleared
Extra Feature Register
all bits cleared
Output signals after reset
Reset state
HIGH
HIGH
HIGH by external pull-up
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