參數(shù)資料
型號(hào): SC16IS741IPW
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述: 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁數(shù): 16/52頁
文件大?。?/td> 382K
代理商: SC16IS741IPW
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
16 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.
Register descriptions
The programming combinations for register selection are shown in
Table 9
.
Table 9.
Register name
RHR/THR
IER
IIR/FCR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
TXLVL
RXLVL
EFCR
DLL
DLH
EFR
XON1
XON2
XOFF1
XOFF2
[1]
MCR[7] can only be modified when EFR[4] is set.
[2]
Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables.
[3]
Accessible only when LCR[7] is logic 1.
[4]
Accessible only when LCR is set to 1011 1111b (0xBF).
Register map - read/write properties
Read mode
Receive Holding Register (RHR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
[1]
Line Status Register (LSR)
Modem Status Register (MSR)
Scratchpad Register (SPR)
Transmission Control Register (TCR)
[2]
Trigger Level Register (TLR)
[2]
Transmit FIFO Level Register
Receive FIFO Level Register
Extra Features Register
divisor latch LSB (DLL)
[3]
divisor latch MSB (DLH)
[3]
Enhanced Feature Register (EFR)
[4]
Xon1 word
[4]
Xon2 word
[4]
Xoff1 word
[4]
Xoff2 word
[4]
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register
FIFO Control Register (FCR)
Line Control Register
Modem Control Register
[1]
n/a
n/a
Scratchpad Register
Transmission Control Register
[2]
Trigger Level Register
[2]
n/a
n/a
Extra Features Register
divisor latch LSB
[3]
divisor latch MSB
[3]
Enhanced Feature Register
[4]
Xon1 word
[4]
Xon2 word
[4]
Xoff1 word
[4]
Xoff2 word
[4]
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