參數(shù)資料
型號(hào): SC16IS741IPW
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述: 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁(yè)數(shù): 18/52頁(yè)
文件大?。?/td> 382K
代理商: SC16IS741IPW
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SC16IS741 internal registers
…continued
S
P
R
1
N
S
S
2
C
[1]
These registers are accessible only when LCR[7] = 0.
[2]
These bits in can only be modified if register bit EFR[4] is enabled.
[3]
These bits are reserved and should be set to 0.
[4]
After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2
×
T
clk
of XTAL1 before reading or writing data to RHR and THR, respectively.
Burst reads on the serial interface (that is, reading multiple elements on the I
2
C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
without de-asserting the CS pin), should not be performed on the IIR register.
[5]
[6]
These registers are accessible only when MCR[2] = 1 and EFR[4] = 1.
[7]
The special register set is accessible only when LCR[7] = 1 and not 0xBF.
[8]
Enhanced Feature Registers are only accessible when LCR = 0xBF.
Enhanced register set
[8]
0x02
EFR
Auto CTS
Auto RTS
special
character
detect
bit 5
bit 5
bit 5
bit 5
enable
enhanced
functions
bit 4
bit 4
bit 4
bit 4
software flow
control bit 3
software flow
control bit 2
software flow
control bit 1
software flow
control bit 0
R/W
0x04
0x05
0x06
0x07
XON1
XON2
XOFF1
XOFF2
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
bit 3
bit 3
bit 3
bit 3
bit 2
bit 2
bit 2
bit 2
bit 1
bit 1
bit 1
bit 1
bit 0
bit 0
bit 0
bit 0
R/W
R/W
R/W
R/W
Table 10.
Register
address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
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