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| 型號： | SC16IS741IPW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
| 中文描述： | 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 382K |
| 代理商： | SC16IS741IPW |
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SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
19 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.1 Receive Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX pin. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
8.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX pin. If
the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow
occurs.
8.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels.
Table 11
shows FIFO Control Register bit settings.
Table 11.
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7] (MSB),
FCR[6] (LSB)
00 = 8 characters
01 = 16 characters
10 = 56 characters
11 = 60 characters
FCR[5] (MSB),
FCR[4] (LSB)
00 = 8 spaces
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
FCR[3]
reserved
FCR[2]
[1]
reset TX FIFO
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
level logic (the Transmit Shift Register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
FCR[1]
[1]
reset RX FIFO
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
level logic (the Receive Shift Register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
FCR[0]
FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
RX trigger. Sets the trigger level for the RX FIFO.
5:4
TX trigger. Sets the trigger level for the TX FIFO.
3
2
1
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16IS741IPW,112 | 功能描述:UART 接口集成電路 IC UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS741IPW,118 | 功能描述:UART 接口集成電路 SINGLE UART W/ 12C-BUS/SPI INTERFC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS741IPW,128 | 功能描述:UART 接口集成電路 IC UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS74Q900 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs |
| SC16IS750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
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