參數(shù)資料
型號: SC16IS741IPW
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
中文描述: 1 CHANNEL(S), 5M bps, I2C BUS CONTROLLER, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁數(shù): 4/52頁
文件大小: 382K
代理商: SC16IS741IPW
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
4 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6.
Pinning information
6.1 Pinning
6.2 Pin description
Table 2.
Symbol
V
DD
CS/A0
a. I
2
C-bus interface
b. SPI interface
Fig 3.
Pin configuration for TSSOP16
SC16IS741IPW
V
DD
A0
XTAL2
XTAL1
A1
RESET
n.c.
RX
SCL
TX
SDA
CTS
IRQ
RTS
I2C
V
SS
002aaf158
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
SC16IS741IPW
V
DD
CS
XTAL2
XTAL1
SI
RESET
SO
RX
SCLK
TX
V
SS
IRQ
CTS
RTS
SPI
V
SS
002aaf159
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Pin description
Pin
1
2
Type Description
-
power supply
I
SPI chip select or I
2
C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip select
pin (Schmitt-trigger, active LOW). If I
2
C-bus configuration is selected
by I2C/SPI pin, this pin along with A1 pin allows user to change the
device’s base address.
I
SPI data input pin or I
2
C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data input pin.
If I
2
C-bus configuration is selected by I2C/SPI pin, this pin along with
A0 pin allows user to change the device’s base address. To select the
device address, please refer to
Table 28
.
O
SPI data output pin. If SPI configuration is selected by I2C/SPI pin,
this is a 3-stateable output pin. If I
2
C-bus configuration is selected by
I2C/SPI pin, this pin function is undefined and must be left as n.c. (not
connected).
I
I
2
C-bus or SPI input clock.
I/O
I
2
C-bus data input/output, open-drain if I
2
C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this pin
is an undefined pin and must be connected to V
SS
.
O
Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register (IER).
Interrupt conditions include: change of state of the input pins, receiver
errors, available receiver buffer data, available transmit buffer space,
or when a modem status flag is detected. An external resistor (1 k
Ω
for 3.3 V, 1.5 k
Ω
for 2.5 V) must be connected between this pin and
V
DD
.
I
I
2
C-bus or SPI interface select. I
2
C-bus interface is selected if this pin
is at logic HIGH. SPI interface is selected if this pin is at logic LOW.
SI/A1
3
SO
4
SCL/SCLK
SDA
5
6
IRQ
7
I2C/SPI
8
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