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參數(shù)資料
| 型號： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
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SST-Melody-DAP
EXECUTIVE KERNEL
INPUT STREAM
OUTPUT STREAM
DECODING LIBRARY
SOFTWARE ARCHITECTURE
The SST-Melody-DAP software programming model has
the following parts:
Executive kernel
Algorithm suite as library modules
The executive kernel has the following functions:
Power-up hardware initialization
Serial port management
Automatic stream detect
Automatic code load
Command processing
Interrupt handling
Data buffer management
Calling library module
Status report
The executive kernel is executed as soon as booting takes place.
“command buffer” and general-purpose programmable flag pins
are initialized. Various data buffers and memory variables are
initialized. Interrupts are programmed and enabled. Then defi-
nite signatures are written “command buffer” to inform the host
that ADSP is ready to receive the commands. Once commands
are issued by host micro, these are executed and appropriate
action takes place. Decoding is handled by issuing appropriate
commands by host micro.
The kernel communicates with the library module for a particu-
lar algorithm in a definite way. The details are found in the
specific implementation documents.
ARCHITECTURE OVERVIEW
The SST-Melody-DAP instruction set provides flexible data
moves and multifunction (one or two data moves with a com-
putation) instructions. Every instruction can be executed in a
single processor cycle. The SST-Melody-DAP assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
A functional block diagram of the SST-Melody-DAP is pro-
vided. The processor contains three independent computational
units: the ALU, the multiplier/accumulator (MAC), and the
shifter. The computational units process 16-bit data directly
and have provisions to support multiprecision computations.
The ALU performs a standard set of arithmetic and logic opera-
tions; division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract opera-
tions with 40 bits of accumulation. The shifter performs logical
and arithmetic shifts, normalization, denormalization, and de-
rive exponent operations.
The shifter can be used to efficiently implement numeric
format control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal
loop counters and loop stacks, the SST-Melody-DAP executes
looped code with zero overhead; no explicit jump instructions
are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is postmodified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five
internal buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
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