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REV. 0
–20–
SST-Melody-DAP
Memory-Mapped Registers (New to the SST-Melody-DAP)
The SST-Melody-DAP has three memory-mapped registers
that differ from other ADSP-21xx Family DSPs. The slight
modifications to these registers (Wait State Control, Program-
mable Flag and Composite Select Control, and System Control)
provide the SST-Melody-DAP’s wait state and BMS control
features. Default bit values at reset are shown; if no value is
shown, the bit is undefined at reset. Reserved bits are shown on
a gray field. These bits should always be written with zeros.
Data Memory (Host Mode)
allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SYSTEM CONTROL
DM(0 3FFF)
RESERVED
SET TO 0
RESERVED, ALWAYS
SET TO 0
PWAIT
PROGRAM MEMORY
WAIT STATES
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0
,
IRQ1
, SCLK
1 = SPORT1
DISABLE
BMS
0 = ENABLE
BMS
1 = DISABLE
BMS
, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
Figure 11. System Control Register
I/O Space (Full Memory Mode)
The SST-Melody-DAP supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit wide data. The lower 11 bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address ranges
as shown in Table IX.
Table IX. Wait States
Address Range
Wait State Register
0x000–1x1FF
0x200–3x1FF
0x400–5x1FF
0x600–7x1FF
IOWAIT0 and Wait State Mode Select Bit
IOWAIT1 and Wait State Mode Select Bit
IOWAIT2 and Wait State Mode Select Bit
IOWAIT3 and Wait State Mode Select Bit
Composite Memory Select (
CMS
)
The SST-Melody-DAP has a programmable memory select
signal that is useful for generating memory select signals for
memories mapped to more than one space. The
CMS
signal
is generated to have the same timing as each of the individual
memory select signals (
PMS
,
DMS
,
BMS
,
IOMS
) but can
combine their functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is
asserted. For example, to use a 32K word memory to act as
both program and data memory, set the
PMS
and
DMS
bits in
the CMSSEL register and use the CMS Pin to drive the chip
select of the memory, and use either
DMS
or
PMS
as the addi-
tional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A “1” in the enable
bit causes the assertion of the CMS signal at the same time as
the selected memory select signal. All enable bits default to 1 at
reset, except the
BMS
bit.
Byte Memory Select (
BMS
)
The SST-Melody-DAP’s
BMS
disable feature, combined with
the CMS pin, allows use of multiple memories in the byte
memory
space. For example, an EPROM could be attached to
the
BMS
select, and an SRAM could be connected to CMS.
Because
BMS
is enabled at reset, the EPROM would be used
for boot
ing. After booting, software could disable
BMS
and set
the CMS signal to respond to
BMS
, enabling the SRAM.
Byte Memory
The byte memory space is a bidirectional, 8-bit wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K 8. The byte
memory space on the SST-Melody-DAP supports read and
write
operations as well as four different data formats. The
byte
memory uses data bits 15:8 for data. The byte memory
uses
data bits 23:16 and address bits 13:0 to create a 22-bit
address.
This allows up to a 4 meg 8 (32 megabit) ROM or
RAM to
be used without glue logic. All byte memory accesses are
timed
by the BMWAIT register and the Wait State Mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16-, or 24-bit word transferred.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BDMA CONTROL
DM(0 3FE3)
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
BDMA
OVERLAY
BITS
Figure 12. BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table X shows the data formats sup-
ported by the BDMA circuit.