- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372283 > SST-MELODY-DAP SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) PDF資料下載
參數(shù)資料
| 型號： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
SST-Melody-DAP
–11–
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip. The two
databuses (PMD and DMD) share a single external databus.
Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the SST-Melody-DAP to fetch two operands in a single
cycle, one from program memory and one from data memory.
The SST-Melody-DAP can fetch an operand from program
memory and the next instruction in the same cycle. In lieu of
the address and databus for external memory connection, the
SST-Melody-DAP may be configured for 16-bit Internal DMA
port (IDMA port) connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSP’s
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG).
One execution mode (Go Mode) allows the SST-Melody-DAP
to continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
The SST-Melody-DAP can respond to 11 interrupts. There can
be up to six external interrupts (one edge-sensitive, two level-
sensitive, and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port, and the power-down circuitry. There is also a mas-
ter RESET signal. The two serial ports provide a complete
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The SST-Melody-DAP provides up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag.
In addition, eight flags are programmable as inputs or out-
puts, and three flags are always outputs.
A programmable interval timer generates periodic interrupts.
A 16-bit count register (TCOUNT) decrements every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit
register (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
Serial Ports
The SST-Melody-DAP incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the SST-Melody-DAP
SPORTs:
SPORTs are bidirectional and have a separate, double buff-
ered transmit and receive section.
SPORTs can use an external serial clock or generate their
own serial clock internally.
SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
SPORTs support serial data-word lengths from three to 16 bits
and provide optional A-law and
μ
-law companding
according to CCITT recommendation G.711.
SPORT receive and transmit sections can generate unique
interrupts on completing a data-word transfer.
SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data-word. An inter-
rupt is generated after a data buffer transfer.
SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this configuration.
PIN DESCRIPTIONS
The SST-Melody-DAP is available in a 100-lead LQFP package
and a 144-ball mini-BGA package. In order to maintain maxi-
mum functionality and reduce package size and pin count, some
serial port, programmable flag, interrupt, and external bus pins
have dual multiplexed functionality. The external bus pins are
configured during RESET only, while serial port pins are soft-
ware configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins. In
cases where pin functionality is reconfigurable, the default state
is shown in plain text; alternate functionality is shown in italics.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST112-T1 | TRANSISTOR J-FET SOT-23 |
| SST113-T1 | TRANSISTOR J-FET SOT-23 |
| SST177-T1 | TRANSISTOR J-FET SOT-23 |
| SST1A1000B | Analog IC |
| SST1A800B | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST-NAS-DN1 | 制造商:Molex 功能描述:DIAG, DEVICENET, NETALYTIX, S/W |
| SSTP600240D25 | 制造商:Teledyne Industrial 功能描述: |
| SSTPAD | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:PICO AMPERE DIODES |
| SSTPAD1 | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:PICO AMPERE DIODES |
| SSTPAD10 | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:PICO AMPERE DIODES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。