- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372283 > SST-MELODY-DAP SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) PDF資料下載
參數(shù)資料
| 型號(hào)： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
–16–
SST-Melody-DAP
FULL MEMORY MODE
HOST MEMORY MODE
SST-Melody-DAP
1/2x CLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0–2
IRQ2
+PF7
IRQE
+PF4
IRQL0
+PF5
IRQL1
+PF6
MODE D/
PF3
MODE C/
PF2
MODE A/
PF0
MODE B/
PF1
ADDR13–0
DATA23–0
BMS
WR
RD
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
SPORT1
SCLK1
RFS1/
IRQ0
TFS1/
IRQ1
DT1/FO
DR1/FI
SERIAL
DEVICE
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
SST-Melody-DAP
CLKIN
1/2x CLOCK
OR
CRYSTAL
SPORT1
SCLK1
RFS1/
IRQ0
TFS1/
IRQ1
DT1/FO
DR1/FI
SERIAL
DEVICE
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
D6/
IRD
D7/
IWR
D4/
IS
D5/IAL
D3/
IACK
IAD15–0
IDMA PORT
SYSTEM
INTERFACE
OR
CONTROLLER
16
IRQ2
+PF7
IRQE
+PF4
IRQL0
+PF5
IRQL1
+PF6
MODE D/
PF3
MODE C/
PF2
MODE A/
PF0
MODE B/
PF1
XTAL
FL0–2
1
16
14
24
A0–A21
DATA
CS
BYTE
MEMORY
ADDR
DATA
CS
I/O SPACE
(PERIPHERALS)
ADDR
DATA
OVERLAY
MEMORY
PM TWO 8K
DM TWO 8K
A0
DATA23–0
BMS
WR
RD
IOMS
A
13–0
D
23–16
D
15–0
A
10–0
D
23–0
A
13–0
D
23–0
Figure 5. Basic System Interface
(such as SCLK, CLKOUT) and timer clock are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the processor’s internal clock and thus its response time
to incoming interrupts. The one-cycle response time of the
standard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the SST-Melody-DAP will remain
in the idle state for up to a maximum of n processor cycles
(n = 16, 32, 64, or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster than can be serviced rate, due to the additional time the
pro
cessor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 5 shows typical basic system configurations with the
SST-Melody-DAP, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-
selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices. The
SST-Melody-DAP also provides four external interrupts and
two serial ports or six external interrupts and one serial port.
Host
Memory mode allows access to the full external databus,
but limits addressing to a single address bit (A0). Through the
use
of external hardware, additional system peripherals can
be
added in this mode to generate and latch address signals.
Clock Signals
The SST-Melody-DAP can be clocked by either a crystal or a
TTL
compatible clock signal. The CLKIN input cannot be
halted, changed during operation, nor operated below the
specified
frequency during normal operation. The only exception
is while
the processor is in the power-down state.
If an external clock is used, it should be a TTL compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external
clock
is used, the XTAL input must be left unconnected.
The SST-Melody-DAP uses an input clock with a frequency
equal to half the instruction rate; a 37.50 MHz input clock yields
a 13 ns
processor cycle (which is equivalent to 75 MHz).
Normally,
instructions are executed in a single processor cycle.
All device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.
Because the SST-Melody-DAP includes an on-chip oscillator
circuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 6. Capacitor values are dependent
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST112-T1 | TRANSISTOR J-FET SOT-23 |
| SST113-T1 | TRANSISTOR J-FET SOT-23 |
| SST177-T1 | TRANSISTOR J-FET SOT-23 |
| SST1A1000B | Analog IC |
| SST1A800B | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST-NAS-DN1 | 制造商:Molex 功能描述:DIAG, DEVICENET, NETALYTIX, S/W |
| SSTP600240D25 | 制造商:Teledyne Industrial 功能描述: |
| SSTPAD | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:PICO AMPERE DIODES |
| SSTPAD1 | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:PICO AMPERE DIODES |
| SSTPAD10 | 制造商:LINEAR 制造商全稱:LINEAR 功能描述:PICO AMPERE DIODES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。