參數(shù)資料
型號(hào)： SST-MELODY-DAP
英文描述： SST-Melody&#174:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02)
文件頁(yè)數(shù)： 15/24頁(yè)
文件大?。?/td> 585K
代理商： SST-MELODY-DAP
REV. 0
SST-Melody-DAP
–15–
Interrupts
The interrupt controller allows the processor to respond to the
11 possible interrupts and reset with minimum overhead. The
SST-Melody-DAP provides four dedicated external interrupt
input
pins:
IRQ2
,
IRQL0
,
IRQL1
, and
IRQE
(shared with the
PF7:4
Pins). In addition, SPORT1 may be reconfigured for
IRQ0
,
IRQ1
, FI, and FO, for a total of six external interrupts.
The
SST-Melody-DAP also supports internal interrupts from
the timer,
the byte DMA port, the two serial ports, software,
and the
power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except power-
down and
RESET
). The
IRQ2
,
IRQ0
, and
IRQ1
input pins can
be pro
grammed to be either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-sensitive and
IRQE
is edge-sensitive. The priori-
ties and vector addresses of all interrupts are shown in Table V.
Table V. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Address (Hex)
Source of Interrupt
Reset (or Power-Up with PUCR = 1)
0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The SST-Melody-DAP masks all interrupts for one instruction
cycle
following the execution of an instruction that modifies
the IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the
IRQ0
,
IRQ1
, and
IRQ2
external interrupts
to be either edge or level-sensitive. The
IRQE
pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0
and
IRQL1
pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are 12 levels deep to allow interrupt, loop, and subroutine
nesting. The following instructions allow global enable or dis-
able servicing of the interrupts (including power-down),
regardless of the state of IMASK. Disabling the interrupts does
not affect serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The SST-Melody-DAP has three low power modes that signifi-
cantly reduce the power dissipation when the device operates
under standby conditions. These modes are:
Power-Down
Idle
Slow Idle
The CLKOUT Pin may also be disabled to reduce external
power dissipation.
Power-Down
The SST-Melody-DAP processor has a low power feature that
lets the processor enter a very low power dormant state through
hardware or software control. Following is a brief list of power-
down features. Refer to the
ADSP-2100 Family User’s Manual
,
“System Interface” chapter, for detailed information about the
power-down feature.
Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the lowest power rating and 200
CLKIN cycle recovery.
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start or
stabilize), and letting the oscillator run to allow 200 CLKIN
cycle startup.
Power-down is initiated by either the Power-Down pin (PWD)
or the software Power-Down Force bit. Interrupt support
allows an unlimited number of instructions to be executed
before optionally powering down. The power-down interrupt
also can be used as a nonmaskable, edge-sensitive interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
The
RESET
pin also can be used to terminate power-down.
Power-Down Acknowledge pin indicates when the processor
has entered power-down.
Idle
When the SST-Melody-DAP is in the Idle mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction. In
Idle mode, IDMA, BDMA, and autobuffer cycle steals still occur.
Slow Idle
The IDLE instruction is enhanced on the SST-Melody-DAP
to let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified
by a selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals
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