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參數(shù)資料
| 型號： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
–4–
SST-Melody-DAP
GENERAL DESCRIPTION
The SST-Melody-DAP is a single-chip microcomputer opti-
mized for digital signal processing (DSP) and other high speed
numeric processing applications.
The SST-Melody-DAP combines the ADSP-2100 family base
architecture (three computational units, data address genera-
tors, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The SST-Melody-DAP integrates 80 Kbytes of on-chip
memory configured as 16K words (24-bit) of program RAM,
and 16K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The SST-Melody-DAP is available in a
100-lead LQFP package and 144-ball mini-BGA.
In addition, the SST-Melody-DAP supports new instruc-
tions, which include bit manipulations—bit set, bit clear, bit
toggle, bit test—new ALU constants, new multiplication
instruction (x squared), biased rounding, result-free ALU
operations, I/O memory transfers, and global interrupt mask-
ing, for increased flexibility. Fabricated in a high speed, low
power, CMOS process, the SST-Melody-DAP operates with a
13.3 ns instruction cycle time. Every instruction can execute in
a single processor cycle.
The SST-Melody-DAP’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle, the SST-Melody-
DAP can:
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
This takes place while the processor continues to:
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
Instruction Set Description
The SST-Melody-DAP assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability.
The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
The syntax is a superset ADSP-2100 family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the
SST-Melody-DAP’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the condition
can be checked and the operation executed in the same
instruction cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
V
DDINT
V
DDEXT
V
INPUT
T
AMB
2.37
2.37
V
IL
= –0.3
0
2.63
3.6
V
IH
= +3.6
+70
2.25
2.25
V
IL
= –0.3
–40
2.75
3.6
V
IH
= +3.6
+85
V
V
V
°
C
Specifications subject to change without notice.
SPECIFICATIONS
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