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參數(shù)資料
| 型號(hào)： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
–2–
SST-Melody-DAP
Mute Play (Voice)
Resume Play (Voice)
Download Voice to Flash
Forward to Next Record
Rewind to Previous Record
Delete a Record
Erase Voice Flash
Version Reporting (G.723.1)
Get G.723.1 Record Information
Rename Voice File
Format Flash
Volume Control
Get Song Name
Get Album Name
Get Singer Name
Get Song Duration
Version Reporting
Supports PC Interface
USB 1.1 Interface
Parallel Port Interface
Other Features:
ID3 Tag Support
SDMI Capable
PERFORMANCE
13.3 ns Instruction Cycle Time @ 2.5 V (Internal)
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
80 Kbytes of On-Chip RAM, Configured as 16K Words
Program Memory RAM
16K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
SYSTEM INTERFACE
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT
Reconfiguration
ICE-Port Emulator Interface Supports Debugging in
Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
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