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參數(shù)資料
| 型號(hào)： | ST63E69D1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR |
| 文件頁數(shù)： | 18/71頁 |
| 文件大?。?/td> | 584K |
| 代理商： | ST63E69D1 |
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Through the programming of the Data RAM Bank
Register (DRBR=E8H) the user can select the
bank or page leaving unaffected the way to ad-
dress the static registers. The way to address the
“dynamic”page is to set the DRBR as describedin
Table 5(e.g.to selectEEPROMpage 0,the DRBR
has to be loaded with content 01H, see Data
RAM/EEPROM addressing for additionalinforma-
tion). Bits0, 1 and 7 of the DRBRare dedicated to
the EEPROM.
The EEPROM pages do not require dedicated in-
structions to be accessedin readingor writing. The
EEPROM is controlled by the EEPROM Control
Register(EECR=EAH). AnyEEPROM location can
be readjustlikeanyotherdatalocation,alsoin terms
of accesstime.
To write an EEPROM location takes an average
time of 5 ms (10ms max) and during this time the
EEPROM is not accessible by the Core. A busy
flag canbe readbythe Coreto knowthe EEPROM
status before trying any access. In writing the
EEPROM can work in two modes: Byte Mode
(BMODE)
and
Parallel
The BMODE is the normal way to use the
EEPROM and consistsin accessingone byte at a
time. The PMODE consists in accessing 8 bytes
per time.
D7.
Not used
SB.
WRITEONLY
.
If this bit is set the EEPROM is
disabled (any
access will be meaningless) and
the
power consumption of the EEPROM is re-
duced tothe leakage values.
Mode
(PMODE).
D5, D4.
Reserved for testingpurposes, they must
be setto zero.
PS.
SETONLY
.
Oncein Parallel Mode,assoonas
the user softwaresets the PSbit the parallel writ-
ing ofthe 8adjacent registerswill start.PS isinter-
nally reset at the end of the programming
procedure. Note that less than8 bytescan be writ-
ten; after parallel programming the remaining un-
defined byteswill have no particular content.
PE.
WRITE ONLY
.
This bit must be set by the
userprogramin orderto performparallel program-
ming (more bytes per time). If PE is set and the
“parallelstartbit”(PS)is low,upto 8adjacentbytes
can be writtenat the maximumspeed, the content
being storedin volatile registers.These 8 adjacent
bytes can be considered as row, whose A7, A6,
A5, A4, A3 are fixed while A2, A1 and A0 are the
changing bytes. PE is automatically reset at the
end of any parallel programming procedure. PE
can be reset by the user software before starting
the programming procedure, leaving unchanged
the EEPROM registers.
BS.
READ ONLY
.
This bitwill be automaticallyset
by the CORE when the user program modifies an
EEPROMregister. The user program has to test it
before any read or write EEPROM operation; any
attemptto accessthe EEPROM while “busybit” is
setwill beabortedandthewriting procedureinpro-
gress completed.
EN
. WRITE ONLY. This bit MUSTbe setto one in
order to write any EEPROM register. If the user
program will attempt to write the EEPROM when
EN= “0” the involved registers will be unaffected
and the ”busy bit”will not be set.
AfterRESETthecontentofEECRregisterwill be00H.
Notes :
When the EEPROM is busy (BS=”1”) the EECR
can notbe accessed inwrite mode, itis onlypossi-
ble to read BS status.This implies that as long as
the EEPROM is busy it is not possible to change
the status of the EEPROMcontrol register. EECR
bits 4 and 5 are reserved for test purposes, and
must never be setto “1”.
Additional Notes on Parallel Mode.
If the user
wants to perform a parallel programming the first
action should betheset to one the PEbit;fromthis
moment the first time the EEPROM will be ad-
dressed in writing, the ROW address will be
latched and it will be possible to change it only at
the endof the programming procedureor byreset-
MEMORY SPACES
(Continued)
EECR
EEPROM Control Register
(EAH, Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
EN = EEPROMEnable Bit
BS =EEPROM Busy Bit
PE =Parallel Mode Enable Bit
PS =Parallel Start Bit
Reserved (Mustbe set Low)
Reserved (Mustbe set Low)
SB =Stand-by Enable Bit
Unused
Figure17. EEPROM Control Register
ST6369
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