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參數(shù)資料
| 型號： | ST63E69D1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機的數(shù)控多FREQUENCYMONITOR |
| 文件頁數(shù)： | 34/71頁 |
| 文件大?。?/td> | 584K |
| 代理商： | ST63E69D1 |
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HWDR
Hardware Activated Watchdog Register
(D8H, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
C = Watchdog ActivationBit
SR = SoftwareReset Bit
T1-T6 = Counter Bits
Figure37. Watchdog Register
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION
(Continued)
T1-T6.
These are the watchdog counter bits. It
should be noted that D7 (T1) is the LSB of the
counter and D2 (T6) is the MSB of the counter,
these bits are in the opposite orderto normal.
SR.
This bit is set to one during the reset phase
and will generate a software reset if cleared to
zero.
C.
This is the watchdog activation bit that is hard-
ware set. The watchdog function is always acti-
vated independentlyofchangesof valueof this bit.
The registerreset value is FEH (Bit 1-7 set to one,
Bit 0cleared).
SERIAL PERIPHERALINTERFACE
The ST6369 Serial Peripheral Interface (SPI) has
been designedto be costeffective and flexible in
interfacing the various peripherals in TV applica-
tions.
It maintains the software flexibility but adds hard-
ware
configurations suitable to drive devices
which require a fast exchange of data. The three
pins dedicated for serial data transfer (single mas-
ter only) can operate in thefollowingways:
- asstandard I/Olines (software configuration)
- as S-BUS or as I
2
CBUS (twopins)
- asstandard (shift register) SPI
When usingthe hardwareSPI,a fixed clockrate of
62.5kHz is provided.
It has to be noted that the firstbit that is output on
the data line bythe 8-bit shiftregisteris the MSB.
SPI Data/Control Registers
For I/O details on SCL (Serial Clock), SDA (Serial
Data) and SEN (Serial Enable) please refer to I/O
Ports description with reference to the following
registers:
PortC data register,AddressC2H (Read/Write).
- BITD0 “SCL”
- BITD1 “SDA”
- BITD3 “SEN”
Port C data direction register, Address C6H
(Read/Write).
SSDR
SPI Serial Data Register
(CCH, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7 = Data Bits
Figure 38. SPI Serial Data Register
D7-D0.
These are the SPI data bits. They can be
neither read nor written when SPI is operating
(BUSY bitset).They are undefinedafter reset.
ST6369
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