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| 型號： | ST63E69D1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR |
| 文件頁數(shù)： | 19/71頁 |
| 文件大小： | 584K |
| 代理商： | ST63E69D1 |
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ting PE without programming the EEPROM. After
the ROWaddress latching the Core can “see” just
one EEPROMrow (the selected one) and any at-
tempt to write or read other rows will produce er-
rors. Donot read the EEPROM while PEis set.
As soon asPEbitis set,the 8volatile ROWlatches
are cleared. From this moment the user can load
data in the whole ROWor just in a subset.PS set-
ting willmodifythe EEPROM registerscorrespond-
ing to the ROW latches accessed after PE. For
example, if the software sets PE and accesses
EEPROMinwriting ataddresses18H,1AH,1BHand
thensetsPS,thesethreeregisterswill bemodifiedat
thesame time;the remainingbyteswill haveno par-
ticular content.Note thatPE is internallyreset at the
endof theprogrammingprocedure.Thisimpliesthat
the user must set PE bit between two parallel pro-
grammingprocedures.Anywaytheusercansetand
thenresetPEwithoutperforminganyEEPROMpro-
gramming. PSis a setonly bitand is internallyreset
at the end of the programmingprocedure.Note that
if theusertries toset PSwhilePEis notsettherewill
not be any programming procedure and the PS bit
will be unaffected.ConsequentlyPS bit can not be
setif ENis low.PScan beaffectedbytheusersetif,
andonly if, ENandPEbitsarealso setto one.
MEMORY SPACES
(Continued)
INTERRUPT
The ST6369 Core can manage 4 different mask-
able interruptsources, plus one non-maskable in-
terrupt source (top priority level interrupt). Each
source isassociated with aparticular interruptvec-
tor that contains a Jump instruction to the related
interrupt service routine. Each vector is located in
the Program Space at a particular address (see
Table 6). When a source provides an interruptre-
quest, and the request processingis alsoenabled
by theST6369 Core,then thePC register isloaded
with the address of the interrupt vector (i.e. of the
Jumpinstruction).Finally,thePCisloaded withthe
address of the Jump instruction and the interrupt
routine is processed.
The relationship between vector and source and
the associatedpriority is hardware fixed for the dif-
ferentST638xdevices.Forsomeinterrupt sources
it is also possible to select by softwarethe kind of
event that will generatethe interrupt.
All interruptscan bedisabled by writingto the GEN
bit (global interruptenable) of the interrupt option
register (addressC8H). Aftera reset,ST6369 is in
non maskable interrupt mode, so no interrupts will
be accepted and NMI flags will be used, until a
RETI instructionis executed.Ifan interruptis exe-
cuted, one special cycle is made by the core, dur-
ing that the PC is set to the related interruptvector
address. A jump instruction at this address has to
redirect programexecution to the beginningof the
relatedinterruptroutine.Theinterrupt detectingcy-
cle, also resets the related interrupt flag (not avail-
able to the user), so that another interrupt can be
stored for this current vector, while its driver is un-
der execution.
If additionalinterruptsarrive fromthesamesource,
they will be lost. NMI can interrupt other interrupt
routines at any time,while other interrupts cannot
interrupt each other. If more than one interrupt is
waiting forservice, they are executed according to
their priority. The lower the number, the higher the
priority. Priority is, therefore, fixed. Interrupts are
checked during the last cycle of an instruction
(RETI included). Level sensitive interrupts have to
be validduring this period.
Table 6
details the
tors/sourcesrelationships.
InterruptVectors/Sources
The ST6369 Core includes 5 different interrupt
vectors in order to branch to 5 different interrupt
routines. The interrupt vectors are located in the
fixed (or static)page ofthe Program Space.
different interrupt vec-
ST6369
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