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參數資料
| 型號： | ST63E69D1 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機的數控多FREQUENCYMONITOR |
| 文件頁數： | 47/71頁 |
| 文件大小： | 584K |
| 代理商： | ST63E69D1 |
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SOFTWARE DESCRIPTION
The ST6369 software has been designed to full y
use thehardwareinthe mostefficientwaypossibl e
whil e keeping byte usage to a minimum; in short
to provide byte efficient programming capability.
The ST6369 Core has the abil ity to set or cl ear
any registeror RAM l ocation bit ofthe Dataspace
with asingle instruction.Furthermore,the program
may branch to a sel ected address depending on
the status of any bit of the Data space. The carry
bit isstored with the val ue ofthe bitwhen the SET
or RES instruction is processed.
Addressing Modes
The ST6369 Core has 9 addressing modes which
are described in the foll owing paragraphs. The
ST6369
Core uses three different address
spaces: Program space, Data space, and Stack
space. Program space contains the instructions
which are to beexecuted, pl us the data for imme-
diate mode instructions. Data space contains the
Accumulator, the X,Y,V and W registers, periph-
eral andInput/Outputregisters,theRAMl ocations
and DataROM locations (forstorageoftabl esand
constants). Stack space contains six 12-bit RAM
cel l s used to stack the return addresses for sub-
routines and interrupts.
Immediate.
In the immediate addressing mode,
the operand of the instruction fol l ows the opcode
l ocation.Astheoperandisa ROM byte,theimme-
diate addressingmode isusedtoaccessconstants
which do not change during program execution
(e.g., a constantused to initial ize a l oop counter).
Direct.
In the direct addressingmode, the address
of the byte that is processed by the instruction is
stored in the l ocation that fol l ows the opcode.
Direct addressing al l ows the user to directly ad-
dress the 256 bytesin Data Spacememory with a
singl e two-byteinstruction.
Short Direct.
The Core can addressthe four RAM
registersX,Y,V,W(l ocations 80H, 81H, 82H, 83H)
in the short-direct addressing mode. In this case,
the instructionis onl y one byte and the sel ection
of thel ocation to be processed is contained in the
opcode. Short direct addressing is a subset of the
direct addressing mode. (Note that 80H and 81H
are al so indirectregisters).
Extended.
In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained byconcatenatingthe four less significant
bits of the opcode with the byte fol l owing the
opcode. The instructions (JP, CALL) that use the
extended addressing mode are abl e to branch to
any addressof the 4K bytes Programspace.
An extended addressing mode instruction is two-
byte l ong.
ProgramCounterRelative.
Therel ativeaddress-
ing mode is onl y used in conditional branch in-
structions.The instruction is used to perform atest
and, if the condition is true, abranchwith aspan of
-15 to +16 l ocations around the address of the
rel ative instruction.If the conditionis not true, the
instruction that fol l ows the rel ative instruction is
executed. The rel ative addressing mode instruc-
tion is one-byte l ong. The opcode is obtained in
adding the three most significant bits that charac-
terize the kind of the test, one bit that determines
whether the branch is a forward (when it is 0) or
backward (when it is 1) branch and the four l ess
significant bitsthat give thespan of the branch (0H
to FH) that must be added or subtracted to the
address of the rel ative instruction to obtain the
address of the branch.
Bit Direct.
In the bit direct addressing mode, the
bit to be set or cl eared is part of the opcode, and
the byte fol l owing the opcode points to the ad-
dress of the byte in whichthe specifiedbit mustbe
set or cl eared. Thus, any bit in the 256 l ocations
of Data space memory can be set or cl eared.
Bit Test & Branch.
The bit test and branch ad-
dressing mode is a combinationof direct address-
ing and rel ative addressing. The bit test and
branch instruction is three-bytel ong. The bit iden-
tification and the tested condition are incl uded in
the opcode byte. The address of the byte to be
tested fol l ows immediatel y the opcode in the
Program space. The third byte is the jump dis-
pl acement, which is in the range of -126 to +129.
This displ acement can be determined using a
l abel , which is converted by the assembler.
Indirect.
In the indirect addressingmode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the
indirect registers, X or Y (80H,81H). The indirect
register is sel ected by the bit 4 of the opcode. A
register indirectinstruction is one byte l ong.
Inherent.
Intheinherent addressingmode,al l the
information necessaryto execute the instruction is
contained in the opcode. These instructions are
one byte l ong.
ST6369
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