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參數(shù)資料
| 型號： | ST63E69D1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR |
| 文件頁數(shù)： | 33/71頁 |
| 文件大小： | 584K |
| 代理商： | ST63E69D1 |
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Figure35. Hardware Activated Watchdog Block Diagram
Figure 36. HardwareActivated Watchdog
Working Principle
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION
The hardware activated digital watchdog function
consistsof a downcounterthatis automaticallyini-
tialized after reset so that this function does not
need to be activated by the user program. As the
watchdog function is always activated this down
counter can not be used as a timer. The watchdog
is using one data space register (HWDR location
D8H). The watchdogregisteris setto FEHonreset
and immediately startsto countdown, requiringno
software start. Similarly the hardware activated
watchdog can not be stopped or delayed by soft-
ware.
The watchdog timecan be programmed using the
6 MSbits in the watchdog register, this gives the
possibility to generate a reset in a time between
3072 to 196608 oscillator cycles in 64 possible
steps.(With a clock frequency of 8MHz this means
from 384
μ
s to 24.576ms).The reset is prevented if
the register isreloaded with the desired value be-
fore bits 2-7 decrement from all zeros to all ones.
The presence of the hardware watchdog deacti-
vates theSTOP instruction and aWAIT instruction
is automaticallyexecuted instead of a STOP. Bit 1
of the watchdog register (set to one at reset) can
be used to generate a software reset if cleared to
zero). Figure 35 shows the watchdog block dia-
gram whileFigure 36 shows its workingprinciple.
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