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參數(shù)資料
| 型號(hào)： | ST63E69D1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR |
| 文件頁(yè)數(shù)： | 20/71頁(yè) |
| 文件大?。?/td> | 584K |
| 代理商： | ST63E69D1 |
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The interruptvectorassociatedwith thenon-mask-
able interruptsource is named interrupt vector #0.
It is located at the (FFCH,FFDH) addressesin the
Program Space.This vector is associatedwith the
PC6/IRINpin.
The
interrupt vectors
(FF6H,FF7H),
(FF4H,FF5H),
(FF0H,FF1H) are named interrupt vectors #1, #2,
#3 and #4 respectively.These vectorsare associ-
ated with TIMER 2 (#1), VSYNC (#2), TIMER 1
(#3) andPC4(PWRIN) (#4).
Interrupt Priority
The non-maskable interrupt request has the high-
est priority and can interrupt any other interrupt
routines at any time, nevertheless the other inter-
rupts cannot interrupt each other. Ifmore than one
interrupt requestis pending,they are processedby
the ST6369 Core according to their priority level:
vector #1 hasthe higherprioritywhile vector#4the
lower. The priority of eachinterrupt sourceis hard-
ware fixed.
located
at addresses
(FF2H,FF3H),
InterruptOption Register
The Interrupt Option Register (IOR register, loca-
tion C8H) is used to enable/disablethe individual
interrupt sourcesand to select theoperating mode
of theexternalinterrupt inputs.Thisregistercan be
addressed in the Data Space as RAM location at
the C8H address, neverthelessit is write-only reg-
ister that can not be accessed with single-bit op-
erations. The operating modes of the external
interrupt inputs associated to interrupt vectors #1
and #2are selectedthrough bits4and 5of theIOR
register.
Figure 18. InterruptOption Register
D7.
Not used.
EL1.
This is the Edge/Level selection bit of inter-
rupt #1.When set to one,the interruptisgenerated
on low level of the related signal; when clearedto
zero,theinterruptisgenerated onfalling edge.The
bit is cleared to zeroafter reset.
ES2.
This is the edge selectionbit on interrupt#2.
ThisbitisusedontheST6369deviceswithon-chip
OSDgenerator for VSYNCdetection.
GEN.
Thisistheglobalenablebit.Whensettooneall
interruptsaregloballyenabled;whenthisbitiscleared
tozeroall interruptsaredisabled(excludingNMI).
D3 - D0.
These bits are not used.
Interrupt Source
Associated
Vector
Vector Address
PC6/IRIN
Pin (1)
Interrupt
Vector # 0 (NMI)
0FFCH-0FFDH
Timer2
Interrupt
Vector # 1
0FF6H-0FF7H
Vsync
Interrupt
Vector # 2
0FF4H-0FF5H
Timer1
Interrupt
Vector # 3
0FF2H-0FF3H
PC4/PWRIN
Interrupt
Vector # 4
0FF0H-0FF1H
Note
: 1. This pin isassociated with the NMI Interrupt Vector
Table 6. Interrupt Vectors/Sources
Relationships
INTERRUPT
(Continued)
IOR
InterruptOption Register
(C8H, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Unused
Unused
GEN =GlobalEnable Bit
ES2 =Edge SelectionBit
EL1 = EdgeLevelSelection Bit
ST6369
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