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參數(shù)資料
| 型號(hào)： | ST63E69D1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR |
| 中文描述： | 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR |
| 文件頁(yè)數(shù)： | 35/71頁(yè) |
| 文件大小： | 584K |
| 代理商： | ST63E69D1 |
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D7-D4.
Thesebits arenot used.
STR.
This is Startbit forI
2
CBUS/S-BUS. This bit is
meaninglesswhen STD/SPIenablebit is clearedto
zero.Ifthisbitis set tooneSTD/SPIbit is also set to
“1” and SPI Start generation, before beginning of
transmission,is enabled.Set tozero after reset.
STP.
This is Stop bitfor I
2
CBUS/S-BUS.This bitis
meaningless when STD/SPI enable bit is cleared
to zero. If this bit is set to one STD/SPI bit is also
set to “1” and SPI Stop condition generationis en-
abled. STP bitmust be reset when standard proto-
col is used (this is also the default reset
conditions).Set to zero after reset.
STD, SPI Enable.
This bit, in conjunctionwith S-
BUS/I
2
CBUS bit, allows the SPI disable and will
select between I
2
CBUS/S-BUS and Standard
shift register protocols. If this bit is set to one, it
selects both I
2
CBUS and S-BUS protocols; final
selection
between
them
BUS/I
2
CBUS bit. Ifthis bit is cleared to zerowhen
S-BUS/I
2
CBUS is set to “1” the Standard shift
register protocol is selected. If this bit is cleared
to ”0” when S-BUS/I
2
CBUS is cleared to 0 the SPI
is disabled.Set to zeroafter reset.
S-BUS/I
2
CBUS Selection.
This bit, in conjunction
with STD/SPI bit, allows the SPI disable and will
select between I
2
CBUS and S-BUS protocols. If
this bitis clearedto“0” when STDbit isalso”0”,the
SPI interfaceisdisabled.Ifthis bitiscleared tozero
when STDbit is set to “1”,the I
2
CBUS protocolwill
be selected. If this bit is set to ”1” when STD bit is
set to “1”, the S-BUS protocol will be selected.
Cleared to zeroafter reset.
Table 10. SPI Modes Selection
is
made
by
S-
SCR1
SPI Control Register 1
(EBH, Write only)
D7 D6 D5 D4 D3 D2 D1 D0
S-BUS/I
2
C BUS Selection
STD/SPIEnable
STP = Stop Bit
STR = Start Bit
Unused
Figure39. SPI Control Register 1
SERIAL PERIPHERAL INTERFACE
(Continued)
D7-D4.
Thesebits are not used.
TX/RX.
WriteOnly.Whenthisbitis set,currentbyte
operation is a transmission. When it is reset, cur-
rent operation is a reception. Set to zero after re-
set.
VRY/S.
Read Only/Write Only. This bit has two dif-
ferent functions in relation to read or write opera-
tion. Reading Operation: when STD and/or TRX
bits is cleared to 0, this bit is meaningless.When
bits STD and TX are set to 1, this bit is set each
time BSY bitis set. This bit is reset during byte op-
eration if real data on SDA line are different from
the output from the shiftregister. Set to zero after
reset. Writing Operation: it enables (if set to one)
or disables (if cleared to zero) the interrupt coming
from VSYNC pin. Undefined after reset. Refer to
OSDdescription foradditional information.
ACN.
Read Only.IfSTD bit(D1 ofSCR1 register)is
cleared to zerothis bitis meaningless.When STD
is setto one,this bitis setto one ifnoAcknowledge
has been received. In this case it is automatically
reset when BSY is set again. Set to zero after re-
set.
BSY.
Read/Set Only.This is the busy bit. When a
one isloaded intothisbit theSPI interfacestart the
transmission of the data byte loaded into SSDR
data register or receiving and building the receive
data into the SSDR data register. This is done in
accordance with the protocol, direction and
start/stop condition(s). This bit is automatically
cleared at the end of the current byte operation.
Cleared tozero after reset.
Note :
The SPI shiftregister is also the data transmission
register andthe data receivedregister;this feature
is madepossible byusingthe serialstructureofthe
ST6369 and thus reducing sizeand complexity.
D1
STD/SP
0
0
1
1
D0
S-BUS/I
2
C BUS
0
1
0
1
SPI Function
Disabled
STDShift Reg.
I
2
C BUS
S-BUS
SCR2
SPIControl Register2
(ECH, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
BSY =Busy Bit0
ACN =Acknowledge Bit
VRY/S = Verify/Sync.Enable
TX/RX =Enable Bit
Unused
Figure 40. SPI Control Register2
ST6369
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