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參數(shù)資料
| 型號： | T7507 |
| 元件分類： | Codec |
| 英文描述： | T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance |
| 中文描述： | T7507四路PCM編解碼器與過濾器，終端阻抗，以及混合平衡 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 558K |
| 代理商： | T7507 |
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14
Lucent Technologies Inc.
Data Sheet
August 1999
Termination Impedance, and Hybrid Balance
T7507 Quad PCM Codec with Filters,
Functional Description
(continued)
Output Word Definition
The status data input on D0 is an 8-bit word of the for-
mat:
NSTAT-Ch0, NTSD-Ch0, NSTAT-Ch1, NTSD-Ch1,
NSTAT-Ch2, NTSD-Ch2, NSTAT-Ch3, NTSD-Ch3
Where:
NSTAT-Ch[0:3] is the wired-OR loop supervision
status of the off-hook detector and ring trip detector
from Channel [0:3].
NTSD-Ch[0:3] is the wire-ORed thermal shutdown
status of the L8567 SLIC and L7583 for Channel
[0:3].
Powerup
This section defines the state of the T7507 when power
is first applied to the device.
T7507
Upon initial application of power, the T7507 is in the
full-chip powerdown state and delayed timing mode.
Output Word
With the initial CSEL, after application of power, all
eight bits of the output word are undefined. With subse-
quent CSEL, all eight bits of the output word will be set
to zero. The output word will remain all 0s until applica-
tion of EN pulses to update the output status informa-
tion. An output word of all 0s implies that all four
channels are in thermal shutdown state and are off-
hook.
EN Status
Upon application of power, all four EN channels will be
at logic 1 (which means that no control data is trans-
ferred to, and no status information is received from,
the SLIC or switch). All EN will remain at logic 1 until
application of an initial FSEP pulse, at which time EN is
created as defined in the Microprocessor Interface sec-
tion of this data sheet.
Input Word—PCM Interface
Upon application of power, the PCM time-slot assign-
ment defaults to the following time-slot assignment:
CH0 Time Slot 0
CH1 Time Slot 1
CH2 Time Slot 2
Ch3 Time Slot 3
Input Word—Relay Control/Timing
Upon application of power, all relay driver control inputs
are forced to logic 0. If the relay driver outputs are tied
to the L8567 relay driver inputs, upon application of an
EN signal, the relay drivers are forced into the off state.
If applied to the L7583 control input, upon application
of an EN pulse, the L7583B is forced into the idle/talk
state.
Input Word—Control Mode
Upon application of power, the receive gain is –3.5 dB
and with the B0/B1 control outputs set to 0/0. Note that
B0/B1 = 0/0, the L8567 SLIC is set into the disconnect
state upon application of EN pulse.
State Definitions
Powerup
All circuits are active. All channels are ready for trans-
mission. EN pulses are generated free-running with
CCLK.
Standby
This mode is programmed on a per-channel basis via
the microprocessor control interface. In this mode, indi-
vidual channels are powered down (not ready for trans-
mission). All reference circuits are always powered up.
EN pulses are generated free-running with CCLK. Ana-
log outputs are held at a nominal 2.35 V.
Full-Chip Powerdown
This is a global parameter; that is, all channels are glo-
bally set into this mode. In this mode, all channels and
all reference circuits are powered down. EN is forced to
logic high. The T7507 is in this state upon application
of power. The T7507 enters this state if FSEP is
removed for four 8 kHz frames. The T7507 will remain
in this state until reapplication of FSEP
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