參數(shù)資料
型號(hào)： T7507
元件分類(lèi)： Codec
英文描述： T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
中文描述： T7507四路PCM編解碼器與過(guò)濾器，終端阻抗，以及混合平衡
文件頁(yè)數(shù)： 2/30頁(yè)
文件大小： 558K
代理商： T7507
2
Lucent Technologies Inc.
Data Sheet
August 1999
Termination Impedance, and Hybrid Balance
T7507 Quad PCM Codec with Filters,
Table of Contents
Contents
Page
Features ......................................................................1
Description...................................................................1
Pin Information ............................................................5
Functional Description.................................................7
PCM Interface ........................................................7
Analog Interface.....................................................8
Transmission Levels...............................................8
Microprocessor Serial Data Control and L8567
SLIC/L7583 Switch (or EMR) Control
Interfaces.............................................................8
Enable Transfers when CCLK Is Bursted
with CSEL ...........................................................9
Enable Transfers when CCLK Is Not
Restricted to CSEL Low.......................................9
Input Word Definition............................................12
Output Word Definition.........................................14
Powerup...............................................................14
T7507..............................................................14
Output Word....................................................14
EN Status........................................................14
Input Word—PCM Interface............................14
Input Word—Relay Control/Timing .................14
Input Word—Control Mode .............................14
State Definitions...................................................14
Powerup..........................................................14
Standby...........................................................14
Full-Chip Powerdown......................................14
Absolute Maximum Ratings.......................................15
Handling Precautions ................................................15
Electrical Characteristics...........................................15
dc Characteristics.................................................15
Transmission Characteristics ....................................16
ac Transmission Characteristics ..........................17
Overload Compression ...................................18
Chip Set Performance Specifications........................21
Gain......................................................................21
Gain Flatness—In Band.......................................21
Gain Flatness—Out of Band—High
Frequencies.......................................................21
Gain Flatness—Out of Band—Low
Frequencies.......................................................22
Loss vs. Level Relative to Loss at –10 dBm
Input at 1020 Hz ................................................22
Return Loss..........................................................22
Hybrid Balance.....................................................22
Microprocessor Interface...........................................23
Timing Characteristics...............................................25
Applications...............................................................28
Outline Diagram.........................................................29
44-Pin PLCC ........................................................29
Ordering Information..................................................30
Figures
Page
Figure 1. Block Diagram............................................ 4
Figure 2. Pin Diagram................................................. 5
Figure 3. Typical Analog Input Section ...................... 8
Figure 4. Overload Compression ............................. 18
Figure 5. Termination Impedance ............................ 21
Figure 6. Transmit and Receive Direction
Frequency-Dependent Loss Relative
to Gain at 3400 Hz ................................... 21
Figure 7. Loss vs. Level ...........................................22
Figure 8. Return Loss ..............................................22
Figure 9. Hybrid Balance......................................... 22
Figure 10. SLIC/Switch Interface Timing .................24
Figure 11. Microprocessor Interface Write
Timing ....................................................24
Figure 12. T7507 Transmit and Receive Timing,
FSEP = 1 MCLK or IFS = 1, Delayed
Timing (D0 = 0) ......................................26
Figure 13. T7507 Transmit and Receive Timing,
FSEP = 1 MCLK or IFS = 1, Nondelayed
Timing (D0 = 1) ......................................26
Figure 14. T7507 Receive Timing, FSEP > 1
MCLK and IFS = 0, Delayed Timing
(D3 = 0) ..................................................27
Figure 15. Typical Frame Sync Timing (IFS = 0) .....27
Figure 16. Basic Loop Start Application Using
the T7507 and the L7583 Switch for
200
+ (680
|| 100 nF) Complex
Termination and Hybrid Balance ............28
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