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參數(shù)資料
| 型號： | T7507 |
| 元件分類： | Codec |
| 英文描述： | T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance |
| 中文描述： | T7507四路PCM編解碼器與過濾器，終端阻抗，以及混合平衡 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大小： | 558K |
| 代理商： | T7507 |
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Lucent Technologies Inc.
5
Data Sheet
August 1999
Termination Impedance, and Hybrid Balance
T7507 Quad PCM Codec with Filters,
Pin Information
5-5347a(F)
Figure 2. Pin Diagram
Table 1. Pin Descriptions
Pin
1
Symbol
FSEP
Type
I
d
Name/Function
Frame Sync Separation.
The pulse width of this 8 kHz signal defines the timing offset
between the transmit and receive frames. If the IFS pin is 0, internally generated receive
frame sync pulses are delayed from the corresponding transmit frame sync pulse rising
edge by one less than the FSEP pulse width in negative MCLK edges. If the pulse width
is one MCLK period or less or if IFS is high, the transmit and receive frame syncs are
made coincident. Loss of FSEP causes the device to power down. A delay of 255 clock
pulses is not allowed. Timing relationships between FSEP and time slot 0 are given in
Figures 12—14. This input is also the frame sync for all the codec filters and PCM inter-
face timing generated from MCLK. An internal pull-down is on FSEP
Digital Ground.
Ground connection for the digital circuitry. All ground pins must be con-
nected on the circuit board.
Transmit PCM Data Output.
This pin remains in the high-impedance state except during
active transmit time slots. An active transmit time slot is defined by programming, FSEP
and the state of IFS. Data is shifted out on the rising edge of MCLK.
Receive PCM Data Input.
The data on this pin is shifted into the device on the falling
edges of MCLK. Data is only entered for valid time slots as defined by the relationship of
the time-slot programming pulse on the FSEP input, and the state of IFS.
Master Clock Input.
The frequency must be 2.048 MHz. This clock serves as the bit
clock for all PCM data transfer. A 40% to 60% duty cycle is required.
Transmit PCM Data Output Flag.
An open-drain output that pulses low during the
period when the D
X
output is enabled.
2
GNDD
—
3
D
X
O
4
D
R
I
5
MCLK
I
6
DxEN
O
39
38
37
36
35
34
33
32
31
30
29
NTSD0
NTSD1
NTSD3
NTSD2
EN0
C
EN1
C
EN3
C
EN2
C
V
DD
VF
X
IN0
AGND0
NTSD
C
NSTAT
C
B1
C
B0
C
RD3
C
RD2
C
RD1
C
V
DD
VF
X
IN2
AGND2
VF
R
ON2
7
8
9
10
11
12
13
14
15
16
17
T7507
6
5
4
3
1
2
44 43 42 41 40
25
18
20 21 22
26 27
19
28
24
23
D
X
E
M
D
R
D
X
G
F
I
C
C
D
D
V
R
O
V
R
O
V
R
O
A
V
X
I
A
V
X
I
V
R
O
V
R
O
V
R
O
V
R
O
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