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參數(shù)資料
| 型號： | T8534 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號處理器 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 890K |
| 代理商： | T8534 |
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12
Agere Systems Inc.
Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
Functional Description
(continued)
The Control Interface
(continued)
Protocol
The format of the command protocol is shown in Fig-
ures 5 and 6.
The control interface operates with one external master
controller and multiple slave codec devices. Each
transfer is initiated by the master, and the slave
responds for either read operations or the fast scan
mode. The slave does not check the bus for activity
prior to transmitting; it only checks for an active CS.
The master should allow for a wait between the end of
a read command until CS becomes active for the read
data. The master must refrain from sending additional
commands to the slave chip until the response is
received. On a 4-wire bus, commands to other devices
may be initiated before the response is received, but
care in generating the CS function is needed to ensure
that the multiple responses do not interfere. It should
be noted that multiple memory locations can be
accessed in the same command by setting the data
field length field to the desired number of bytes to be
transferred. If flow control is desired, it must be per-
formed by using separate commands, each transfer-
ring smaller blocks of information, or by controlling the
serial clock (gapping the serial clock), or with CS in the
case of byte-by-byte mode.
There is no response from the slave to the master for a
write operation. The response to a read operation sim-
ply includes the data to be read in the data field. This
data is sent least significant bit first, with the bytes sent
in ascending sequence. Commands from the master
controller include data for write operations, but not for
read operations. Since the coefficients and gains are
stored in volatile memory, all the coefficients and gains
must be loaded after powerup. There is, however, no
need to reload them when switching from active to
standby modes, or vice versa. Great care should be
exercised in loading memory when the codec channel
is not in standby mode. Sudden changes in the termi-
nation or balance impedances can result in undesirable
system operation.
All data is transmitted in a byte-oriented fashion with
the least significant bit of each byte transferred first.
Multibyte fields are transferred least significant byte
first in both directions. The data field will contain the
first addressed data location first, with subsequent data
locations transmitted in ascending order.
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