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參數(shù)資料
| 型號(hào)： | T8534 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號(hào)處理器 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 890K |
| 代理商： | T8534 |
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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
14
Agere Systems Inc.
Functional Description
(continued)
The Control Interface
(continued)
Write Command
A write command is used to write to the memory addresses. Figures 7—10 illustrate normal or byte-by-byte opera-
tion with continuous or gapped DCLKs. For gapped DCLK operation, transitions, not frequency, are critical (as long
as transitions occur no faster than 122 ns apart).
0078
* Two or more full DCLK cycles are required before the start of a new command frame.
Note: Data field length of 1 shown.
Figure 7. Write Operation, Normal Mode (Continuous DCLK)
0076
Notes:
Data field length of 1 shown.
CK1 through CK4 are additional DCLK pulses required to properly process the data.
CK3 and CK4 are not necessary if another command frame follows this sequence.
Figure 8. Write Operation, Normal Mode (Gapped DCLK)
COMMAND FRAME
0
1
7
0
1
7
CS
DCLK
DI
COMMAND
START ADDRESS
DATA
0
1
7
0
1
7
0
1
7
0
1
7
LENGTH
0
1
7
0
1
7
*
COMMAND FRAME
0
1
7
0
1
7
CS
DCLK
DI
COMMAND
START ADDRESS
DATA
0
1
7
0
1
7
0
1
7
0
1
7
C
C
C
C
LENGTH
0
1
7
0
1
7
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