參數(shù)資料
型號(hào)： T8534
英文描述： T8533/34 Quad Programmable Line Card Signal Processor
中文描述： T8533/34四線(xiàn)卡可編程信號(hào)處理器
文件頁(yè)數(shù)： 18/48頁(yè)
文件大?。?/td> 890K
代理商： T8534
Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
18
Agere Systems Inc.
Functional Description
(continued)
The Control Interface
(continued)
Read Command
(continued)
0075
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait
≥
1.5
μ
s after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DATA.
The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK
cycles are required to process the read data.
Two or more DCLK cycles are required before the start of a new command frame.
Note: Data field length of 1 shown.
Figure 13. Read Operation, Byte-by-Byte Mode (Continuous DCLK)
0
1
7
0
1
7
CS
DCLK
DI
COMMAND
START
ADDRESS
LENGTH
DATA
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
*
COMMAND FRAME
ONE OR MORE FULL DCLK
CYCLES REQUIRED HERE
D0
0
1
7
WAIT
≥
1.5
μ
s
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