參數(shù)資料
型號(hào): T8534
英文描述: T8533/34 Quad Programmable Line Card Signal Processor
中文描述: T8533/34四線卡可編程信號(hào)處理器
文件頁(yè)數(shù): 40/48頁(yè)
文件大?。?/td> 890K
代理商: T8534
Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
40
Agere Systems Inc.
Software Interface
(continued)
Table 18. Control Bit Definitions
(continued)
Control Name
(Address, Decimal)
[Address, Hex]
RXBITOFF
(130)
[0x82]
Bit
Assignments
Function
5—7
Receive direction bit offset for the FS signal. Defaults to 0. These 3 bits
can be thought of as the least significant bits (RXOFF contains the more
significant bits) of a bit counter that determines the location of the first bit
of the PCM data from FS.
Load as 0.
Receive time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits, allow for two time slots when using linear
mode.
Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of
2 (6 dB). 0 dB is the maximum recommended setting.
Gain adjustment for tweak gain stage in receive direction. Defaults to
0x01ac (
7.58 dB). This is an 11-bit multiply operation with a maximum
gain of 2 (6 dB). 0 dB is the maximum recommended setting.
Load as 0s.
Peak detector tweaking control. Use default
of 4.
0—4
0—7
RXOFF
(131)
[0x83]
GRX1
(132—133)
[0x84—0x85]
GRX2
(134—135)
[0x86—0x87]
NORMCTRL
(136)
[0x88]
0—10
0—10
6—7
3—5
Bit Number
5
4
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit Number
2
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Function
(dB)
0.0
3.01
6.02
9.03
12.04
15.05
18.06
21.07
Function
(dBm0)
57
54
51
48
45
42
39
36
3
0
1
0
1
0
1
0
1
0—2
Far-end speech detector threshold. Use
default of 5.
0
0
1
0
1
0
1
0
1
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